Previous talks

Titles:

(1) Formal verification of an indigenous real-time operating system, by Meenakshi D'Souza

(2) Exploring Alias Analysis Based Optimizations Missed by the Compiler, by Khushboo Chitre

Time: 21 March 2023, 19:00 - 20:00 India Standard Time, by Zoom

Host: Raveendra Kumar Medicharla, TCS Research

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Abstracts

(1) Real-time Operating Systems (RTOSs) are widely used to design and develop embedded safety critical software applications. Such applications have to be fault tolerant, deterministic and meet stringent safety standards which include several functionality-related real-time requirements, The applications rely on and use several features of the underlying RTOS to satisfy these design requirements. Real-time operating systems provide kernel APIs and scheduling algorithms to cater to many of the safety requirements. We will discuss our experience of formally verifying several safety critical requirements of one such indigenous RTOS that has time and space partitioning features and is being used by the Indian avionics industry.

(2) Context-sensitive inter-procedural alias analyses are more precise than intra-procedural alias analyses. However, they are not scalable for large real-world applications. As a consequence, most production compilers sacrifice precision for scalability and opt for intra-procedural alias analysis. Alias analysis is used by many compiler optimizations, including loop transformations. Due to the imprecision of alias analysis, the program’s performance may suffer, especially in the presence of loops. Previous work proposed a general approach based on code-versioning with dynamic checks to disambiguate pointers at runtime. However, the overhead of this approach is high. Other suggested approaches with low overheads can only be applied to loops with certain constraints. In this work, we present our technique implemented in a LLVM-based tool named, Scout, that can disambiguate two pointers at runtime using single memory access. Scout can disambiguate array accesses within a loop for which the approaches with low overhead cannot be applied. The key idea of Scout is to constrain the allocation size and alignment during memory allocations. In addition, Scout uses feedback from static optimizations to reduce the number of dynamic checks needed for optimizations. Our technique enabled new opportunities for loop-invariant code motion, dead store elimination, loop vectorization, and load elimination in an already optimized code.

Related publication:

Title: The Road Not Taken: Exploring Alias Analysis Based Optimizations Missed by the Compiler

Venue: The ACM SIGPLAN Object Oriented Programming Systems Languages and Applications (OOPSLA'22)

Speaker biographies:

(1) Meenakshi is a Professor of Computer Science at IIIT Bangalore where she teaches courses on Software Testing, Design and Analysis of Algorithms, Computability, Discrete Mathematics and Graph Theory. Meenakshi's research interests are in Formal Methods and Software Testing, as applied to safety critical embedded software. Meenakshi is also interested in gender diversity in Computer Science. Meenakshi is the Secretary cum Treasurer and a Council Member of ACM India, and an Associate Editor of Sadhana, a journal of the Indian Academy of Sciences. Her Software Testing course is being offered on the NPTEL platform for the sixth year and has had more than 55,000 learners across these years. Meenakshi has sponsored research projects from the Royal Academy of Engineering, UK, DST, DRDO HQ, Siemens and CEFIPRA-DST.

(2) Khushboo is a full time Ph.D. (CSE) scholar at IIITD, working with Dr. Piyus Kedia and Dr. Rahul Purandare. Her research is supported by the prestigious TCS Research fellowship under the TCS Research Scholar Program. Her research focuses on developing approaches that explores alias analysis based optimization opportunities missed by the compilers. She completed her M.Tech. in Computer Science and Engineering from Indraprastha Institute of Information Technology (IIIT) Delhi in 2020. Her research interests lie in the area of Compiler Design and Program Analysis.

Titles:

(1) Data-lite Machine Learning, by Shrikanth Narayanaswamy Chandrasekaran

(2) A Semi-automated Approach to Generate an Adaptive Quality Attribute Relationship Matrix, by Unnati Shah

Time: 21 Feb 2023, 19:00 - 20:00 India Standard Time, by Zoom

Host: Raghu Reddy, IIIT Hyderabad

Abstracts

(1) Software Engineering practitioners and researchers often suffer from the data-hungry presumption that more data is inherently better. A recent study identified a startling trend among 240 open-source GitHub projects with 1.2 million commits (changes). We find that the information (software defects) in those projects ""clump"" towards the earliest parts of the project. Therefore, a machine learning model built only from the first 150 commits once predicted post-release defects for the rest of the project life-cycle. Such a data-lite process performed on par or better than the state-of-the-art alternatives.

Hence, if data has the most information in some small region, perhaps a model learned from that region would suffice for the rest of the project. Using this data-lite approach, we can build machine learning models quickly and importantly early in the project life cycle.

ICSE 2021 - https://arxiv.org/pdf/2011.13071.pdf. Early Life Cycle Software Defect Prediction. Why? How?

(2) [Context/Motivation] A critical success factor in Requirements Engineering (RE) involves recognizing conflicts in Quality Requirements (QRs). Nowadays, Quality Attributes Relationship Matrix (QARM) is utilized to identify the conflicts in QRs. The static QARM represents how one Quality Attribute (QA) undermines or supports to achieve other QAs.

[Question/Problem] However, emerging technology discovers new QAs. Requirements analysts need to invest significant time and non-trivial human effort to acquire knowledge for the newly discovered QAs and influence among them. This process involves searching and analyzing a large set of quality documents from literature and industries. In addition, the use of static QARMs, without knowing the purpose of the QRs in the system may lead to false conflict identification. Rather than taking all QAs, domain-specific QAs are of great concern for the system being developed.

[Principal ideas/results] In this paper, we propose an approach which is aimed to build an adaptive QARM semi-automatically. We empirically evaluate the approach and report an analysis of the generated QARM. We achieve 85.67% recall, 59.07% precision and 69.14% F-measure to acquire knowledge for QAs.

[Contributions] We provide an algorithm to acquire knowledge for domain-specific QAs and construct an adaptive QARM from available unconstrained natural language documents and web search engines.

Publication Venue: REFSQ 2020: Requirements Engineering: Foundation for Software Quality, pp 239–256

Speaker biographies:

(1) Shrikanth is a Ph.D. (Computer Science) graduate from NC State (Advised by Dr. Tim Menzies) with ten years of industry experience. He has a research interest in Software Engineering (software defect prediction) and Machine Learning. He is employed full-time with Oracle America, Inc to build tools to improve developer experiences for next-generation cloud infrastructure. Previously, he was a Technology R&D Specialist at Accenture Labs, Software Engineering group India. Before that, he was a Software Engineer and Senior Systems Engineer at ABB India Ltd and Infosys Ltd. In the last two summers, he interned (research) at Fujitsu Laboratories of America and Microsoft.

He is an engineering graduate with a track record of innovations (3 granted patents) and published papers at premier avenues.

Website: https://snaraya7.github.io/

(2) Unnati Shah is an assistant professor in the department of computer science at Utica University, New York, USA. She completed her doctorate from NIT, Surat. Her research focuses resolving ambiguities and specification of Non-functional requirements.

Titles:

(1) Leveraging Program Structures & Learning-based Techniques to Improve Type-4 Code Clone Detection Techniques

(2) BiRD: Race Detection in Software Binaries under Relaxed Memory Models.

Speakers: (1) Nikita Mehrotra (2) Ridhi Jain

Time: January 17th 2023, 19:00 - 20:00 India Standard Time, by Zoom

Abstracts

(1) Code clones are duplicate code fragments that share (nearly) similar syntax or semantics. Code clone detection plays an important role in software maintenance, code refactoring, and reuse. A substantial amount of research has been conducted in the past to detect clones. A majority of these approaches use lexical and syntactic information to detect clones. However, only a few of them target semantic clones. Recently, motivated by the success of deep learning models in other fields, including natural language processing and computer vision, researchers have attempted to adopt deep learning techniques to detect code clones. These approaches use lexical information (tokens) and(or) syntactic structures like abstract syntax trees (ASTs) to detect code clones. However, they do not make sufficient use of the available structural and semantic information, hence limiting their capabilities. This work addresses the problem of semantic code clone detection using program dependency graphs and graph neural networks, leveraging the program structured syntactic and semantic information. This talk is based on the following accepted paper: Modelling Functional Similarity in Source Code with Graph-based Siamese Neural Networks Venue: TSE Journal First, 2021.

(2) Instruction reordering and interleavings in program execution under relaxed memory semantics result in non-intuitive behaviors, making it difficult to provide assurances about program correctness. Several static analyses approaches exist, but studies have shown that up to 90% of the concurrency bugs reported by state-of-the-art static analyzers are false alarms. As a result, filtering false alarms and detecting real concurrency bugs is a challenging problem. Unsurprisingly, this problem has attracted the interest of the research community over the past few decades. Nonetheless, many of the existing techniques rely on analyzing source code and rarely consider theeffects introduced by compilers, and assume a sequentially consistent memory model. In a practical setting, however, developers often do not have access to the source code, and even commodity architectures such as x86 and ARM are not sequentially consistent. In this work, we present BiRD, a prototype tool, to dynamically detect harmful data races in x86 binaries under relaxed memory models, TSO and PSO. BiRD employs {\em source-DPOR} to explore all distinct feasible interleavings for a multithreaded application. Our evaluation of BiRD on 42 publicly available benchmarks and its comparison with the state-of-the-art tools indicate BiRD's potential in effectively detecting data races in software binaries.

Speaker biographies:

(1) Nikita Mehrotra is a PhD candidate at Program Analysis Group, IIIT-Delhi, working with Dr. Rahul Purandare. Her research is supported by PM fellowship with Nucleus Software as industry partner. Her research interest lies at the intersection of deep learning and software engineering. Her current research focuses on improving type-4 code clone detection techniques.

(2) Ridhi Jain is Security Researcher at the Technology Innovation Institute (TII), Abu Dhabi, working on the efficient identification of vulnerabilities in software. She is also a Ph.D. candidate at IIIT-Delhi, working with Prof. Rahul Purandare in the areas of Program Analysis, Software Binary Analysis, and Software Verification. Ridhi's research focuses on verifying concurrent software under relaxed memory models, TSO and PSO. She is also interested in developing dependable tools to provide safety assurances for software binaries. Her projects have resulted in publications in reputed Software Engineering venues and patents. She will serve as a PC member for ISEC 2023 and has served as a sub-reviewer for various SE conferences.

Title: Preventing Failures Caused by Breaking Changes in JavaScript Libraries

Speaker: Anders Møller, Aarhus University

Time: December 20th 2022, 19:00 - 20:00 India Standard Time, by Zoom

Abstract: JavaScript libraries often evolve, and breaking changes can cause failures in the applications that use the libraries. With the extensive use of libraries in modern JavaScript software development and the dynamic nature of the language, this is a major concern for many application developers. In this talk, I'll present the JSFIX tool that automates the process of adapting JavaScript code to breaking changes by the use of novel program analysis technology.

Speaker bio: Anders Møller is a professor at Aarhus University and manager of the Center for Advanced Software Analysis. He has received a Consolidator Grant from the European Research Council (ERC), the Danish Elite Research Prize 2020, and six times a Distinguished Paper Award from ACM SIGSOFT or SIGPLAN. He is currently an associate editor of ACM TOPLAS and ACM TOSEM. His main research area is program analysis, specifically for JavaScript.

Title: Software Engineering: A Methodology for Reliable Software

Speaker: Vineeth Paleri

Time: November 15th 2022, 19:00 - 20:00 India Standard Time, by Zoom

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Abstract: Programming, even today, is more of an art where most people learn only by watching others perform and through habit, with little direction as to the principles involved. Here we stress the need for conscious application of programming principles to produce reliable software. Reliable programs are no more a luxury in many critical areas. Unreliable software can cause severe harm to the society, including loss of lives. The proposed software engineering methodology emphasizes on Specification and Design before Coding. The methodology uses Separation of Concerns as the key principle to address complexity of problems. The methodology also adopts a Modular Design strategy to control the complexity of software with Procedural Abstraction and Data Abstraction as the basic principles behind it. The approach takes the view that software as a product is not just the code but a package consisting of the Specification, the Program, and the Proof that the program meets the specification.

Speaker bio:

Education:

Doctor of Philosophy (August 1994 - July 1999), Department of Computer Science and Automation, Indian Institute of Science, Bangalore.
Master of Technology (August 1984 - January 1986), Department of Computer Science and Engineering, Indian Institute of Technology, Kanpur.
Bachelor of Engineering (Electrical) (1976 - 1981), Department of Electrical Engineering, National Institute of Technology, Calicut (Formerly Regional Engineering College, Calicut).

Professional Appointments:

Professor (August 2005 - Present), Department of Computer Science and Engineering, National Institute of Technology, Calicut.
Visiting Assistant Professor (January 2003 - December 2003), Department of Computer Sciences, Purdue University, West Lafayette, USA.
Visiting Assistant Professor (January 2002 - December 2002), Department of Computer and Information Science, Indiana University Purdue University, Indianapolis, USA.

Research Interests: Programming, Program analysis, and Code optimization.

Title: The Development of our Static Worst Case Execution Time (WCET) Analysis Technique

Speaker: Reinhard Wilhelm

Time: October 18th 2022, 19:00 - 20:00 India Standard Time, by Zoom

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Abstract: The talk tells the development story of our single-core WCET-analysis technology, our starting points, the principles of our solution, the underlying techniques, the illusions we had about the commercial impact, the overall effort needed for the development of an almost completely new formal method. It will touch upon research results about timing predictability of architectures and end in a sobering view of the current situation where industry has switched to using multi-core architectures where no solution to the WCET-analysis problem exists. The Underlying publication: Reinhard Wilhelm: Real time spent on real time. Commun. ACM 63(10): 54-60 (2020).

Speaker bio: Reinhard Wilhelm is a Professor Emeritus at Saarland University. Reinhard studied mathematics and informatics in Münster, München and Stanford, and received his Dr. rer.nat. 1977 from TU München. He was professor for Informatics at Saarland University from 1978 until 2014. He served as Scientific Director of the Leibniz Centre for Informatics at Schloss Dagstuhl from 1990 until 2014. His research areas are compiler construction, static program analysis, real-time embedded systems, and software visualization. He coauthored several textbooks on programming languages and on compiler construction. He, together with 5 PhD students founded the company AbsInt, producer of tools for software quality-assurance aimed at safety-critical embedded systems.

Reinhard received Test-of-Time Awards at the international conference ESWEEK 2019 for the long-term impact of his research on execution time bounds and from the IEEE TCRTS for his publication R. Heckmann, M. Langenbach, S. Thesing, R. Wilhelm: The influence of processor architecture on the design and the results of WCET tools, Proc. IEEE 91(7): 1038-1054 (2003) in 2022. IEEE TCRTS bestowed on him the Outstanding Innovation and Leadership Award in 2021.

Title: The Missing Piece of Test Automation Puzzle: Explainable Deep Oracles

Speaker: Reyhaneh Jabbarvand

Time: September 20th 2022, 19:00 - 20:00 India Standard Time, by Zoom

Abstract: Given an input to the software, the challenge of distinguishing the expected, correct behavior from the incorrect one is called the test oracle problem. The absence of automated test oracles demands human to decide whether observed behavior and generated output is correct, increasing the cost of testing to a great extent. Furthermore, it demonstrates a significant bottleneck that not only inhibits test automation and uptake of automated testing mechanisms, but also complicates debugging, i.e., root causing the bug found through testing and fixing it. The more expressive and informative is the decision of the test oracle, i.e., explains why a decision is made, the more effective and efficient localizing detected bugs and fixing them is. In this talk, I will introduce the concept of Explainable Deep Oracles. Such oracles not only overcome the test oracle challenge, but also bridge the gap between testing and debugging, integrating software reliability assurance pipeline.

Speaker bio: Reyhaneh Jabbarvand is an Assistant Professor of Computer Science at the University of Illinois, Urbana-Champaign. Her current research focuses on explainable neural software analysis, including (1) the use of explainable neural models to enhance software analysis and (2) leveraging software analysis techniques to improve the reliability of neural software, including ML-intensive mobile apps and self-driving software systems. Her research has been supported by Google (Google Ph.D. Fellowship for her work on advancing energy testing of mobile applications), IBM (AI-Powered Testing and Debugging for Microservices), and C3.ai (Cyber safety Cage for Networks). She has also been recognized as a rising star in EECS by UIUC in 2019.

Title: Specification-Guided Component-Based Synthesis from Effectful Libraries

Speaker: Ashish Mishra

Time: August 16th 2022, 19:00 - 20:00 India Standard Time, by Zoom

Abstract: Component-based synthesis seeks to build programs using the APIs provided by a set of libraries. Often, these APIs have effects (like mutating states) which make it challenging to reason about the correctness of potential synthesis candidates. This is because changes to the global state made by effectful library procedures affect how they may be composed together. This will yield an intractably large search space that can confound typical enumerative synthesis techniques. If the nature of these effects are exposed as part of their specification, however, deductive synthesis approaches can be used to help guide the search for components.

In this talk, I will present a new specification-guided synthesis procedure that uses Hoare-style pre- and post-conditions to express fine-grained effects of potential library component candidates to drive a bi-directional synthesis search strategy. The procedure alternates between a forward and a backward search process. The forward search seeks to build larger terms given an existing context but is otherwise unaware of the actual goal. The backward search mechanism seeks terms consistent with the desired goal but is otherwise unaware of the context from which these terms must be synthesized. To further improve efficiency and scalability, we integrate a conflict-driven learning procedure into the synthesis algorithm that provides a semantic characterization of previously encountered unsuccessful search paths that are used to prune the space of possible candidates as synthesis proceeds.

We have implemented our ideas in a tool called Cobalt, and in the talk, I will demonstrate its effectiveness on several challenging synthesis problems defined over OCaml libraries equipped with effectful specifications.

(Based on a recent work with Suresh Jagannathan, conditionally accepted at OOPSLA' 22)

Speaker bio: Ashish Mishra is a Postdoctoral Researcher at Purdue University working with Prof Suresh Jagannathan in the areas of Programming Languages, Program Verification and Program Synthesis. Before this, he worked for a year on Program Analysis for JS with Prof Frank Tip. He finished his PhD at Indian Institute of Science, India, under the supervision of Prof. Y. N. Srikant.

He is interested in developing techniques and tools to help developers build reliable, secure and efficient Software. In this context, he is especially interested in building Program Analysis and Verification tools, designing Domain Specific Programming Languages, and developing Automated Program Synthesis techniques for programs with effects, dynamic features and asynchronous semantics.

Besides Programs, Ashish is interested in politics, law, history and books, particularly Biographies. He is also interested in applying technology to policy and social problems and is currently involved with several Indian NGOs.

Talk 1 : Utilizing Persistence for Post Facto Suppression of Invalid Anomalies Using System Logs, by Seema Nagar

Talk 2: Handling Memory Pointers in Communication between Microservices, by Vini Kanvar

Time: July 19th 2022, 19:00 - 19:30 India Standard Time for Talk 1, and 19:30 - 20:00 India Standard Time for Talk 2, by Zoom

Abstract 1: The robustness and availability of cloud services are becoming increasingly important as more applications migrate to the cloud. The operations landscape today is more complex, than ever. Site reliability engineers (SREs) are expected to handle more incidents than ever before with shorter service-level agreements (SLAs). By exploiting log, tracing, metric, and network data, Artificial Intelligence for IT Operations (AIOps) enables detection of faults and anomalous issues of services. A wide variety of anomaly detection techniques have been incorporated in various AIOps platforms (e.g. PCA and autoencoder), but they all suffer from false positives. In this paper, we propose an unsupervised approach for persistent anomaly detection on top of the traditional anomaly detection approaches, with the goal of reducing false positives and providing more trustworthy alerting signals. We test our method on both simulated and real-world datasets. Our technique reduces false positive anomalies by at least 28%, resulting in more reliable and trustworthy notifications. (Based on a paper accepted in ICSE '22 NIER Track.)

Abstract 2: When microservices are written from scratch, APIs are usually made stateless. However, when an existing monolith application is decomposed into microservices, it may not be possible to make all the APIs stateless. Therefore, objects transferred via APIs may contain pointers. Consequently, data transfer via an API i.e., from a client address space to a server address space, reconstruction at the server, and returning to the client become non-trivial operations. Conventionally, data transfer between microservices is done using JSON, which serializes pointers to values that they point to. Once the data in JSON reaches the server, deserialization creates objects of the original types on the server. However, deserialization is unable to return the same objects passed by the client because serialization leads to loss of pointer information. We propose to apply pointer swizzling to solve this problem. Pointer swizzling modifies the definition of the class by introducing ID of the object and by replacing all pointers with IDs of the objects it refers. These IDs help to maintain correct reference in the server. After the server API operates on the objects, the server returns new objects of the same types to the client. These new objects need to be plugged back in the client address space i.e., pointers to the old objects in the client need to now point to the corresponding new objects. This plugging back is non-trivial because we do not know how the old objects map to the new objects. We propose creating memory maps at runtime to overcome this challenge. (Based on a paper accepted in ICWS '22).

Speaker bio 1: Seema Nagar is a staff research scientist at IBM Research India. She has been researching the field of computer science for the last fifteen years. She has over 40 publications in eminent conferences and journals and more than 150 patents filed. She has been named a master inventor for two consecutive terms. She has also been part of the reviewer committee of many eminent conferences, such as IJCAI, NAACL, IEEE Cloud and ACL. She has earned several Research Awards in IBM Research India, including three Outstanding Technical Achievement Awards for her work on social network analysis and trustworthy AI. She actively mentors several researchers/students at the research lab. She obtained her B. Tech. and M. Tech. in Computer Science and Engineering from IIT, Guwahati in 2007, and IIT, Delhi in 2011 respectively. Currently, she is also pursuing a part-time PhD from IIIT, Guwahati.

Speaker bio 2: Vini Kanvar is a Research scientist at IBM Research, India working on application modernization and refactoring monolith applications to microservices. She has obtained her PhD (Computer Science) on static analysis of dynamically allocated data from IIT Bombay. Vini has authored patents and has presented her research in forums like Microsoft Research Lab, TCS Research Lab, ACM Grad Cohort at IIT Delhi, ACM Computing Surveys, Cadence Simulation Group, Synopsys Verification Group, International Symposium on Memory Management at Barcelona, and International Conference on Data Management.

Title: (Greybox) Fuzz Testing

Abstract: Fuzz testing, initially proposed by Barton Miller, is a popular technology for finding bugs in software systems via (biased) random search over the domain of inputs. In this talk, we will review the technology of fuzz testing - specifically its variants in the form of blackbox, greybox and whitebox fuzzing. We will discuss coverage based greybox fuzzing, which conducts a biased random search over inputs guided by a fitness function to approximate code coverage. Greybox fuzzing is dominant method for finding security vulnerabilities in software systems, today. Recent developments in fuzzing such as directed fuzzing to reach specific code locations, and smart fuzzing to test applications processing structured data will be discussed. Overall, we will discuss the pro-s and con-s of fuzzing technology and take a forward looking view where it can be tuned to find deeper bugs such as violations of linear-time temporal logic (LTL) properties. The talk, while providing an overview of the area, will outline some of the key works in the area conducted in my team at NUS on greybox fuzzing. Mainly in our works, we proposed looking inside the greybox fuzzers --- while bringing in ideas from symbolic execution and model checking without risking the efficiency of fuzzing. Therefore, throughout the talk, we may allude to connections of fuzzing technology to symbolic execution, and/or model checking.

Speaker bio: Abhik Roychoudhury is a Provost's Chair Professor of Computer Science at the National University of Singapore, where he has been since 2001 after receiving his Ph.D. in Computer Science from the State University of New York at Stony Brook in 2000. He is the current Director of the National Satellite of Excellence in Trustworthy Software Systems at Singapore. He has also helped set up the Singapore Cyber-security Consortium. Abhik's research focuses on software testing and analysis, software security and trust-worthy software construction. His research team is known for contributions to automated program repair, and fuzz testing, and he (jointly with Cristian Cadar) received the IEEE New Directions Award in 2022 for contributions to symbolic execution. Abhik is a member of the Steering committee of the flagship conferences in Software Engineering, International Conference on Software Engineering (ICSE) and Symposium on Foundations of Software Engineering (FSE). His former doctoral students have been placed in various universities as faculty members, including Peking University, University College London, Max-Planck Institute, University of Melbourne, and other places.

Time: June 21st 2022, 19:00 India Standard Time, by Zoom

Title: Teaching software architecture

Abstract: Students understand coding. And the simplest way to make a student understand architecture is to make him write architecture code. To realize that some of the programming we do, goes, not into business logic, but into supporting quality requirements seems to be the easiest first step to appreciate what architecture is. So a series of programming assignments implementing ‘tactics’ for quality attributes is what we found the best way to teach software architecture issues.

Software architecture is taught as part of a Software Engineering and sometimes as a full course even. Design patterns is a favorite thing that seems to be discussed often. However, tactics are more atomic and a design pattern is often implementing some tactics. We found that the sequence (1) Quality attributes (2) tactics for quality (3) coding exercises to implement tactics (4) patterns, is a good learning trail for software architecture.

Given that teaching architecture in a classroom is challenging, and that it is best learnt through mentoring and an apprenticeship, we sketch a possible syllabus and some assignments in a course on architecture for students and fresh recruits.

Speaker bio: Dr TV Prabhakar is an Emeritus Fellow in the CSE Department at IIT Kanpur having taught there for more than 35 years. Software architecture and online education are his areas of interest at this point.

Time: May 17th 2022, 19:00 India Standard Time, by Zoom

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