Reliability Modeling of FinFET and its Application in Circuit Design:

A Device Circuit Co-Design

Aim

To implement source/drain, channel engineering to improve reliability of the device.


Objectives

  1. First, a novel FinFET device structure will be proposed using the source/drain, channel engineering to improve reliability of the device. Further, spacers of the invention also play an important role in the reliability. Therefore, device will also optimize using spacer engineering.

  2. The device structure will be further modified using 3rd, and 4th group materials and these are used in oxide, gate and source/drain engineering for the reliability.

  3. Further, NBTI will be analysis and device optimized for reliable design.

  4. To optimize the device for increased reliability, soft computing techniques will be adopted as used in my previous research work.

  5. Reliability models are proposed for long channel FinFET device and are not incorporated the 3rd and 4th group material effects hence reliability model will be proposed for nanoscale device dimension.

  6. Stress and recover model will also require for circuit design because mitigation techniques are proposed using then. Therefore total stress recovery model will also be proposed.

SERB