Computer Science

Software Production

[Bayesian Econometrics] Stochastic Volatility Model Estimation with Flexible Normal Mixture MCMC (written in C /C++)
[Computer Architecture] Razor Computer Architecture Simulator: Circuit Level Correction of Timing Errors and for Low-Power Operation (written in C/C++)

U.S. Patent 

Recovery from errors in a data processing apparatus, U.S. Patent Number: 20050207521.

Computer Science Publication

Self-Tuning DVS Processor Using Delay-Error Detection and Correction (with S.Das; D. Roberts; D. Blaauw; T. Austin; T. Mudge; and K. Flautner). Journal of Solid State and Circuits (JSSC). 2005.

A Self-Tuning DVS Processor Using Delay-Error Detection and Correction (with S. Das; D. Roberts; D. Blaauw; T. Austin; T. Mudge; and K. Flautner). Symposium on VLSI Circuits. 2005. 

Razor: Circuit Level Correction of Timing Errors and for Low-Power Operation (with D. Ernst; S. Das; D. Blaauw; T. Austin; T. Mudge; N. Kim; and K. Flautner). Micros Top Picks, IEEE MICRO Journal. November/December, Volume 24, Number 6, 2004. 

Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming (with S. Das; T. Pham; T. Austin; D. Blaauw; and T. Mudge). International Symposium on Low Power Electronics and Design (ISLPED-2004). August 2004. 

Circuit-Aware Computer Architecture Simulator (with S. Das; V. Bertacco; T. Austin; D. Blaauw; and T. Mudge). 41st Design Automation Conference (DAC-2004). June 2004.