Date: November 19 (Wednesday), 2025
Time: 12:15PM - 1:15PM (Central)
Room: 230
Link to SC25 BOF page
Special invited speakers: Mark Ren (NVIDIA), Lilia Zaourar (CEA), and Toru Niina (RIKEN)
Session leaders: Kazutomo Yoshii (ANL), Kentaro Sano (RIKEN), and John Shalf (LBNL)
As the demand for performance and energy efficiency rises in the post-Moore era, this BOF session explores the transformative role of domain-specific accelerators and open-source hardware tools for HPC and scientific edge computing. Join us as we examine emerging trends, challenges, and opportunities in architecture research and chip prototyping.
Topics
Trends & Challenges: Identify emerging trends such as chiplet, challenges, and future needs in architecture research.
Open-Source Tools: Introducte open-source hardware tools and designs, share user experiences, and conduct a gap analysis of current open-source tools.
HPC-powered chip development: Redirect the computational demands of chip prototyping and multi-physics simulations to HPC
AI-Assisted Design: Explore how AI is accelerating the chip development process (e.g., RTL design, verification, PR, design check, layouting, etc).
Collaboration: Build a network of professionals in architecture design, chip prototyping, and open-source hardware tools. Ongoing architecture research within the HPC community
Relevance
This session is particularly relevant for architecture researchers, simulator developers, and professionals working with EDA tools and AI-assisted designs. Despite the potential, the adoption of open-source tools in HPC remains limited, making this discussion crucial for driving innovation and efficiency in chip design processes.
Expected Outcomes
Participants will gain actionable insights into the current and future landscape of HPC architecture research. The session aims to inspire new initiatives, foster collaboration, and identify strategies to overcome existing challenges in the field. Attendees will leave with a deeper understanding of how specialized accelerators and open-source tools can optimize HPC workloads and drive forward architecture innovation.