Presenters

Michael Voss is a Principal Engineer in the Intel Architecture, Graphics and Software Group at Intel. He is a co-author of the recently released book Pro TBB: C++ Parallel Programming with Threading Building Blocks and is a technical leader in the Parallel Runtimes Engineering team that develops oneAPI’s Threading Building Blocks (oneTBB) and the Data Parallel Library (oneDPL). Mike was the architect of the Intel® Threading Building Blocks (Intel® TBB) flow graph API, a C++ API for expressing dependency, streaming, and data flow applications. He has coauthored over 40 published papers and articles on topics related to parallel programming, and frequently consults with customers across a wide range of domains to help them effectively use the threading libraries provided by Intel. Mike actively participates in the C++ Standard Committee.

Rafael Asenjo is Professor of Computer Architecture at the University of Malaga. He obtained a PhD in Telecommunication Engineering in 1997. He has been using TBB since 2008 and over the last five years, he has focused on productively exploiting heterogeneous chips leveraging TBB as the orchestrating framework. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to research into CPU+FPGA chips while visiting the University of Bristol. He served as General Chair for ACM PPoPP'16 and as an Organization Committee member as well as a Program Committee member for several HPC related conferences (PPoPP, SC, PACT, IPDPS, HPCA, EuroPar, and SBAC- PAD). His research interests include heterogeneous programming models and architectures, parallelization of irregular codes and energy consumption. Along with Michael Voss and James Reinders he co-authored the latest book (open access) on Threading Building Blocks (Pro TBB).