Publications

Journal Articles

1. Simulation and Comparative study of Resonant Tunneling Diode, Isha KAPOOR, Purva SINGHVI, Yashvi SHAH, Babita BIRUA and Rutu PAREKH, Walailak Journal of Science and Technology, 2021.

2. Comparative study of Double Gate and Silicon on Insulator MOSFET by varying device parameters Dax PATEL, Soham SOJITRA, Jay KADIA, Bhavik CHAUDHARY, Rutu PAREKH,, Trends in Sciences, 2021. 10.48048/tis.2022.3216

3. Shah, R., Parekh, R., & Dhavse, R. (2021). Design strategy and simulation of single-gate SET for novel SETMOS hybridization, J Comput Electron. 10.1007/s10825-020-01622-2

4. Shah, C., Shah, R., Dhavse, R., & Parekh, R. (2021). Design and Implementation of Single Electron Transistor Based 8X8 bit Signed Multipliers, Materials Today: Proceedings. 12-09-2019

5. Pathade, T., Agrawal, Y., Parekh, R., & Palaparthy, V. (2021). Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects, Material Today : Proceedings., 10.1016/j.matpr.2020.12.1182

6. Jethwa, B., Panchasara, M., Zanzarukiya, A., & Parekh, R. (2021). Realtime Soldier's Health Monitoring system Incorporating low power LoRa communication, International Journal of Sensor Networks.

7. Pathade, T., Agrawal, Y., Parekh, R., & Kumar, G. (2021). Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization, IEEE Transactions on Nanotechnology.

8. Patel, R., Agarwal, Y., & Parekh, R. (2020). A New Tool for Simulation of Single Electron Transistor based Microprocessor Using Vector File, Nanoscience & Nanotechnology-Asia, 10(4), 493–500., 10.2174/2210681209666191014122904

9. Patel, R., Agrawal, Y., & Parekh, R. (2020). Single-electron transistor: review in perspective of theory, modelling, design and fabrication, Microsystem Technologies, 10.1007/s00542-020-05002-5

10. Patel, R., Agrawal, Y., & Parekh, R. (2019). Design of prominent SET-based high performance computing system, IET Circuits, Devices & Systems, 14(2), 159–167. 10.1049/iet-cds.2019.0166

11. Parekh, R. (2019). Design and simulation of single electron transistor based SRAM and its memory controller at room temperature, International Journal of Integrated Engineering, 11(6), 186–195. 12-09-2019,

12. Patel, R., Agrawal, Y., & Parekh, R. (2019). A novel slice-based high-performance ALU design using prospective single electron transistor, IETE Journal of Research, 10.1080/03772063.2019.1642803

13. Patel, N., Agrawal, Y., & Parekh, R. (2018). Novel subthreshold modelling of advanced on-chip graphene interconnect using numerical method analysis, IETE Journal of Research, 10.1080/03772063.2018.1528189

14. Parekh, R., Beauvais, J., & Drouin, D. (2014). SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit, Microelectronics Journal, 45(8), 1087–1092. 10.1016/j.mejo.2014.05.020

15. Parekh, R., Beaumont, A., Beauvais, J., & Drouin, D. (2012). Simulation and design methodology for hybrid SET-CMOS integrated logic at 22-nm room-temperature operation, IEEE transactions on electron devices, 59(4), 918–923. 10.1109/TED.2012.2183374

Conference Publications

1. Tanya Gaurav, Krutarthkumar Patel and Rutu Parekh, RTL to GDSII Implementation of RADIX-4 Booth Multiplier, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

2. Siddharth Deshpande, Shein Sopariwala, Ritvik Singhvi, Raghav Khandelwal, Jigarkumar Marvaniya and Rutu Parekh, Performance Analysis of Silicon Nanowire FET for GAA and Pi Gate Configurations, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

3. Neha Jain, Pragya Maheshwari, Saumya Aghera, Idika Mittal, Deval Sonani, Marmik Sileshkumar Prajapati and Rutu Parekh, Analysing the Effects of Varying Parameters in a MESFET, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

4. Vidhi Pala, Vishank Makhe, Khyati Bhuva and Rutu Parekh, RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

5. Nishit Nathwani, Aditya Joshi and Rutu Parekh, RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL), 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

6. Jaykumar Dave, Mohmadsohil Momin, Chirayu Sheth, Rushabh Gajab, Meet Dadhania, Priya Patel and Rutu Parekh CNTFET: Comparative Study of Planar and Coaxial, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

7. Akshar Joshi, Milan Nagariya, Aniket Vyas, Param Modi, Mahiraj Rathod, Richa Patel and Rutu Parekh, Parameterized Comparison of Carbon Nanotube and Graphene Nanoribbon Field Effective Transistor, 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO 2022), Kerela, India, April 2022. Accepted.

8. Shubham Purohit, Yash Agrawal, Rutu Parekh, Bakul Gohel and Vinay Palaparthy, Capacitive Electrode Based Single Lead ECG Detection System, 8th International Conference on Signal Processing and Integrated Networks (SPIN 2021), India.

9. Shubham Purohit, Prashant Laddha and Rutu Parekh, Implementation and Physical Design of 8/4-Bit Signed Divider, 8th International Conference on Signal Processing and Integrated Networks (SPIN 2021), India.

10. Takshashila Pathade, Yash Agrawal, Rutu Parekh and Girish Mekala, CNTFET Based Low Power Repeaters for On-Chip Interconnect System, VDAT 2021, India.

11. Yatin Kumar Gupta, Yash Agrawal, Rutu Parekh, Bakul Gohel, Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design, VDAT 2021, India.

12. Radhika J. Kachhadiya, Yash Agrawal, Rutu Parekh, Implementation of ALU using RTL to GDSII flow and on NEXYS 4 DDR FPGA board, ICESC 2021, India.

13. Tanya Gaurav, Amit Bhatt, Rutu Parekh, Design and Implementation of low power RISC V ISA based coprocessor design for Matrix multiplication, ICESC 2021, India.

14. Kaushal Parmar, Dharmin Solanki, Jaydeep Sangada, Rutu Parekh, Accident Detection and Notification System Using AWS, ICESC 2021, India.

15. Hunny Bulani , Parth Darji , Rishi Sanghvi , Abhishek Kalavadiya, Rutu Parekh, Performance Analysis of a Single Junction Crystalline Solar Cell using 1Drift Diffusion Modelling, ICESC 2021, India.

16. Romil Joshi; Prutha Shaherawala; Krishna Rana;Krupa Joshi; Rutu Parekh, Performance Analysis of UTB and Nanowire Tunnel FET by varying various Device Intrinsic Parameters, ICESC 2021, India

17. Abhishek Kalavadiya, Rutu Parekh, Sanghamitra Banik, Rachesh Trivedi and Yash Agrawal, A Single Electron Transistor Based Floating Point Multiplier Realization at Room Temperature Operation, ET2ECN, India

18. Patel, V., Rajput, P., Zanzarukiya, A., Parekh, R. (2020). Real-time Globally Accessible Accident Notifications and Tracking for the Motor-Vehicles, MCCS.

19. Kumar, H., Porwal, A., Devre, H., Jethwa, M., Dhavse, R., Parekh, R. (2020). Effect of different channel material on the performance parameters for FinFET device, MCCS.

20. Jethwa, M., Devre, H., Agrawal, Y., Parekh, R. (2020). A Comparative study of MOSFET (Single and Double Gate), Silicon Nanowire FET, and CNTFET by varying the Oxide Thickness, MCCS.

21. Jethwa, B., Panchasara, M., Zanzarukiya, A., & Parekh, R. (2020). Realtime Wireless Embedded Electronics for Soldier Security. In 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) (pp. 1–6).

22. Rajput, P., & Parekh, R. (2020). On-Board Diagnostics based remote emission test for Light Motor Vehicles. In 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) (pp. 1–6).

23. Shah, R., Parekh, R., & Dhavse, R. (2020). Strategy for Designing Single Electron Transistors. In International Conference on Emerging Technology Trends in Electronics Communication and Networking (pp. 44–57).

24. Zanzarukiya, A., Jethwa, B., Panchasara, M., & Parekh, R. (2020). Assistive Hand Gesture Glove for Hearing and Speech Impaired. In 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184) (pp. 837–841).

25. Trivedi, R., Banik, S., Patel, P., Agrawal, Y., & Parekh, R. (2020). Design of prominent Time-to-Digital Converter using single electron transistor operating at room temperature. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–5).

26. Patel, T., Jain, A., Gameti, D., Patel, U., & Parekh, R. (2020). Remote Structural Health Monitoring System for Bridges. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–4).

27. Borisagar, P., Jani, S., Agrawal, Y., & Parekh, R. (2020). An Efficient and Compact Review of Face Recognition Techniques. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–5).

28. Agrawal, Y., Parekh, R., Palaparthy, V., & others (2020). Automated E-circuit Designing and Characterization using Prominent Neural Network. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–5).

29. Jani, S., Patel, P., Divakar, B., Patel, V., & Parekh, R. (2020). Cloud based Accident Detection and Notification System. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–5).

30. Patel, N., Agrawal, Y., Parekh, R., & Kumar, M. (2020). Variability Analysis of On-chip Graphene Interconnects at Subthreshold Regime. In 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) (pp. 1–6).

31. Patel, R., & Parekh, R. (2019). DNA Based Hybrid Circuit Design Approaches. In 2019 IEEE 5th International Conference for Convergence in Technology (I2CT) (pp. 1–6).

32. Kalirathinam, K., Rathod, H., Agrawal, Y., & Parekh, R. (2019). Real-Time Crowd Detection and Surveillance System Using an Arduino Based Flight Controller for Quadcopters. In International Conference on Innovation in Modern Science and Technology (pp. 872–879).

33. Kaushik, H., Zanzarukiya, A., Jethwa, B., Agrawal, Y., & Parekh, R. (2019). Real-Time Human Detection & Tracking System Incorporating MEMS Technology. In 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) (pp. 1–6).

34. Borisagar, P., Agrawal, Y., & Parekh, R. (2018). Efficient Vehicle Accident Detection System using Tensorflow and Transfer Learning. In 2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS) (pp. 1–6).

35. Patel, R., Agrawal, Y., & Parekh, R. (2018). A vector file generation program for simulating single electron transistor based computing system. In 2018 IEEE Electron Devices Kolkata Conference (EDKCON) (pp. 647–650).

36. Agrawal, Y., Chandel, R., Girish, M., & Parekh, R. (2018). Contemporary On-chip System Modeling using FDTD in Low Power Regime. In 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) (pp. 1–3).

37. Pathade, T., Shah, U., Agrawal, Y., & Parekh, R. (2018). Preeminent buffer insertion technique for long advanced on-chip graphene interconnects. In 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) (pp. 1–3).

38. Agrawal, Y., Chandel, R., & Parekh, R. (2017). Performance Evaluation of On-chip Global Interconnects in DSM Technology using Different Signaling Techniques, ICET: EITM-2017

39. Joshi, R., Parekh, R., & Agrawal, Y. (2017). Design and optimization of single electron transistor based 4-bit arithmetic and logic unit at room temperature operation. In 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (pp. 34–39).

40. Etzkorn, J., Xuan, W., Jouvet, N., Beaumont, A., Baboux, N., Souifi, A., Calmon, F., Bounouar, M., Guilmain, M., Parekh, R., & others. Single Electron Device Model Library for Hybrid Circuit Design.

41. Griveau, D., Ecoffey, S., Parekh, R., Bounouar, M., Calmon, F., Beauvais, J., & Drouin, D. (2012). Single electron CMOS-like one bit full adder. In 2012 13th International Conference on Ultimate Integration on Silicon (ULIS) (pp. 77–80).

42. Etzkorn, J., Xuan, W., Jouvet, N., Beaumont, A., Baboux, N., Souifi, A., Calmon, F., Bounouar, M. A., Guilmain, M., Parekh, R., Ecoffey, S. and Drouin, D. (2011). Library of Single Electron Device Models for CMOS Hybrid Circuit Design, 4ème colloque du Laboratoire International Associé : Nanotechnologies & Nanosystèmes, Allevard-les-Bains, France.

43. Parekh, R. (2009). Simulation, Design & Fabrication of Single Electron Memory Circuit, CMC Annual Symposium, TEXPO Research Competition, Ottawa, ON, Canada.

44. Beaumont, A., Dubuc, C., Morissette, J.-F., Guilmain, M., Parekh, R., Ecoffey, S., Calmon, F., Souifi, A., Baboux, N., Monfray, S., Beauvais, J. and Drouin, D. (2009). A back-end SED fabrication platform for hybrid SED-CMOS integration, 2 ème Colloque du Laboratoire International Associé Nanotechnologies & Nanosystèmes, Anse, France.

Book Chapters

1. Shubham Tomar, Het Sutar, and Rutu Parekh, RTL to GDSII: Fully Digital Indirect Time of Flight SoC, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021,

2. Achal Parikh, Arpit Chaudhari, Jay Patel and Abhishek Bhowmik, Rutu Parekh, Analysis of Graphene Field-Effect Transistor (GFET) as a Sensor, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

3. Ayush Nirwal, Rushabh Agrawal, Ragini Meena, Aayush Raval, Akash Paramar and Rutu Parekh, Effects of structural parameters on the performance of vertically aligned carbon nanotube arrays as a thermal interface material, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

4. Parth Katrodiya, Keval Thakarar, Dhruvam Panchal, Hitarth Bharad, Jaimin Vaghela, Sai Deepak and Rutu Parekh, Performative analysis on Ion Sensitive Field Effect Transistor by varying intrinsic parameter, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

5. Shubham Tomar and Rutu Parekh, Phase Frequency Detector using CNTFET at 16nm node, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

6. Tirth Patel, Rutu Parekh, Nishtha Diwanji, Michika Gayari, Himadri Patel and Kinjal Patel, Analysis and Simulation of Various Parameters of Mixed CNT Bundle for Interconnect Applications, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

7. Anmol Saxena, Vyom Saraf and Rutu Parekh ASIC Implementation of a 16-bit Brent Kung Adder at 45nm GSC Technology Node, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

8. Abhishek Pandya, Harshita Anand and Rutu Parekh, A Complete ASIC Design Implementation of Content Addressable Memory from RTL to GDSII, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

9. Isha Desai, Jhanvi Shroff and Rutu Parekh, Performance Analysis of DGFET, MESFET, and SOI on Varying Device Intrinsic Input Parameters, Springer Lecture Notes in Electrical Engineering, International Conference on Sustainable Technology and Advanced Computing in Electrical Engineering (ICSTACE), India, November 2021.

10. Strategy for Designing Single Electron Transistors, R. Shah, R. Parekh and R. Dhavse, 3rd International Conference on EMERGING TECHNOLOGY TRENDS in ELECTRONICS COMMUNICATION and NETWORKING, India, February 07 - 08, 2020.

11. Design of prominent single precision 32-bit floating point adder using single electron transistor operating at room temperature, Sharma, A., Dhavse, R., Agrawal, Y., Parekh, R., Springer lecture notes on electrical engineering, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), SVNIT, India.

12. Smart Soldier Health Monitoring System Incorporating Embedded Electronics, Teja, K., Patel, U., Patel, P., Agrawal, Y., Parekh, R., Springer lecture notes on electrical engineering, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), SVNIT, India.

13. Island Engineering of Single-Electron Transistor for Room Temperature Operation, Shah, R., Parekh, R., Dhavse, R., Springer lecture notes on electrical engineering, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), SVNIT, India.

14. Prospective Incorporation of Booster in Carbon Interconnects for High Speed Integrated Circuits, Pathade, T., Agrawal, Y., Parekh, R., Girish, M., Springer lecture notes on electrical engineering, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), SVNIT, India.

15. Variability Analysis of On-Chip Interconnect System using Prospective Neural Network, Misra, A., Agrawal, Y., Palaparthy, V., Parekh, R., Springer lecture notes on electrical engineering, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), SVNIT, India.

16. Real-time Crowd Detection and Surveillance System Using an Arduino Based Flight Controller for Quadcopters, Kalirathinam, K., Rathod, H., Agrawal, Y., Parekh, R., Springer Book Series: Learning and Analytics in Intelligent Systems (LAIS), ICIMSAT-2019, India.

17. Prospective current mode logic for on chip interconnects in integrated circuit design, Agrawal, Y., Chandal, R., Kumar, G., Parekh, R., in book titled: IET VLSI and Post-CMOS Devices, Circuits and Modelling, 2018.

18. Design and Implementation of Autonomous UAV Tracking System Using GPS and GPRS, Thakkar, D., Rajput, P., Dubey, R., and Parekh, R., ICACIE, 2017 - Best Springer paper award in Intelligent Networking Track.

19. Modeling and simulation of 1/f noise during threshold switching for Phase Change Memory, Parekh, R., Shojaei, M., and Rajendran, B., Lecture Notes in Electrical Engineering (LNEE), Springer, ICACCP, 2017.

20. Noise removing filters and its implementation on FPGA, Mishra, A. and Parekh, R., Lecture Notes in Electrical Engineering (LNEE), Springer, ICACCP, 2017.

21. Single Precision Floating Point Matrix Multiplier using Low Power Arithmetic Circuits, Gargave, S., Agrawal, Y., and Parekh, R., Lecture Notes in Electrical Engineering (LNEE), Springer, ETAEERE, 2016.

22. Performance Analysis of Current-mode Interconnect System in Presence of Process, Voltage and Temperature Variations, Agrawal, Y., Parekh, R., and Chandel, R., Lecture Notes in Electrical Engineering (LNEE), Springer, ETAEERE, 2016.

Presentations and Poster

1. Strategy for Designing Single Electron Transistors, R. Shah, R. Parekh and R. Dhavse, 3rd International Conference on EMERGING TECHNOLOGY TRENDS in ELECTRONICS COMMUNICATION and NETWORKING, India, 23 July 2020, 10.1007/978-981-15-7219-7_5

2. Nanoélectronique à un électron : fabrication, caractérisation et simulation, Beaumont, A., Dubuc, C., Parekh, R., Morissette, J.F., Guilmain, M., Al Hadi, R., Markey, P., Beauvais, J. et Drouin, D., 1st Workshop Laboratoier International Associè, Nano-technologies & Nanosystèmes”, Estrimont, Mont Orford, Québec, Canada, 2008.

3. Simulation and Design of Hybrid SET-CMOS circuit, prepared by Parekh R., presented by Drouin, D., Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Le Château Frontenac, Québec, Canada, 2011.

Paper Article

Strategy for Designing Single Electron Nanotechnology in Dairy and Food Industry, Dr. Rutu Parekh, Dairy times, A Group Publication of Advance Info Media and Events, May-June 2016