Professional Experiences
Professional Experiences
Department of Electrical and Computer Engineering
University of Wisconsin-Madison
Aug 2024-present
Florida Institute for Cyber Security Research (FICS Research)
University of Florida
Aug 2022-Aug 2024
Researching microchip, nanoscale, and Hardware Security, physical attack on IC.
Analog Circuit Design and Automation
Neural Semiconductor Limited
Feb 2020-July 2022
• Completed 10 tape-out till now in 12nm, 22nm, 28nm, and 45nm FinFET and Silicon on Insulator (SOI) process.
• Industrially experienced in virtuoso skill scripting for Circuit & Layout Automation with SKILL Script.
• Simulation, post-layout extraction flow, and EDA tools automation and scripting.
• Industrially experienced in the full flow of Analog and Mixed-Signal IP design with 12nm, 22nm, 28nm, 45nm SOI process node; functional simulation (Pre layout Simulation); Analog Layout design with proper device matching concept; Post Layout Simulation;
• Worked in 101 & 301 stage ring Oscillator Layout Design and Post Simulation of 13 different Standard cells like AOI22, OAI22, Buffer, and Nand2 with Counter and Driver block in 12nm, 22nm, 28nm, 45nm Process. Automated full-chip schematic, layout generation with SKILL Script and python.
• Industrially experienced in the full flow of digital signal ASIC, VLSI design with 45nm & 90nm process node; RTL simulation; RTL synthesis; physical design layout, floor plan, power plan, placement, clock tree synthesis, and routing.
• Designing analog IP e.g., differential Op-amp, two-stage Op-amp, Driver circuit, Band Gap Reference (BGR) with 22nm SOI process.
• Experienced in 12nm, 22nm, 28nm, 45nm, and 90nm process nodes.
• Developed an in-house CV sorting software with Java Spring boot.
IEEE SPS & IEEE ComSoc Joint Student Branch Chapter, AUST
April 2019-February 2020
IEEE SPS & IEEE ComSoc Joint Student Branch Chapter, AUST
February 2019-April 2019
Member, IEEE
Member, IEEE Signal Processing Society
Member, IEEE Computer Society