Publications

Google Scholar

Patents

1. "Semiconductor package and method of forming the same", by R. Weerasekera, S. Bhattacharya, K. F. Chang, and V. S. Rao. (2019, Feb. 7). US20190043792A1. 

Research Papers

1. Q. Tang, D. Pamunuwa and R. Weerasekera, "DT2HDL: A Binary Decision Tree to HDL Generation tool", accepted for ISQED 2025

2. V. Marot, M. B. Krishnan, M. K. Kulsreshath, E. Worsey, R. Weerasekera and D. Pamunuwa, "Nanoelectromechanical Binary Comparator for Edge-Computing Applications", DATE 2025

3. R. Maccay and R. Weerasekera, “Machine Learning Assisted Postural Movement Recognition using Photoplethysmography(PPG),” Nov. 02, 2024, arXiv: arXiv:2411.11862. doi: 10.48550/arXiv.2411.11862. 

4. D. Uduwawala, and R. Weerasekera, "Incident and Load Power Relations in a Mismatched Lossless Transmission Line ", Accepted for Springer Circuits Systems, Signal Processing, 2024 May

5. D. Uduwawala, R. Weerasekera and A. Gunawardena, "Complex Impedance Transformation Using Symmetric Coupled Microstrip Lines of Adjusted Electrical Lengths," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 14, no. 3, pp. 461-470, March 2024, doi: 10.1109/TCPMT.2024.3352137 

6.  R. Mayne, N. Roberts, N. Phillips, R. Weerasekera, A. Adamatzky, "Propagation of electrical signals by fungi", Biosystems, 10.1016/j.biosystems.2023.104933 , 2023

7.  N. Phillips, R. Weerasekera, N. Roberts and A. Adamatzky, “Electrical signal transfer characteristics of mycelium-bound composites and fungal fruiting bodies”, accepted for Fungal Ecology, 2023 

8.  L. Jeniks, and  R. Weerasekera, "Sport-Related Back Injury Prevention with a Wearable Device", Biosensors and Bioelectronics: X, 2022, https://doi.org/10.1016/j.biosx.2022.100202

9.  T. C. Draper, N. Phillips, R. Weerasekera, R. Mayne, C. Fullarton,  B. P. J. de Lacy Costello and A. Adamatzky, ''Contactless Sensing of Liquid Marbles for Detection and Characterization", Lab-on-Chip, Vol. 20, No. 1, pp. 136-146, 2020.  

10.  R. Mayne, T. C. Draper, N. Phillips, J. G. H. Whiting, R. Weerasekera, C. Fullarton, B. P. J. de Lacy Costello and A. Adamatzky, ''Neuromorphic Liquid Marbles With Aqueous Carbon Nanotube Cores", In Langmuir, vol. 35, no. 40, pp. 13182-13188, 2019.

11.  A. Adamatzky, N. Phillips, R. Weerasekera, M.-A. Tsompanas, and G. Ch. Sirakoulis, ''Street map analysis with excitable chemical medium", In Physical Review E, vol. 98, no. 1, 2018.

12.  R. Weerasekera, G. Katti, R. Dutta, J. Zhou and S. Bhattacharya, "An Analytical Capacitance Model for Through-Silicon Vias (TSVs) in Floating Silicon Substrate" In IEEE Transactions on Electron Devices, vol.~63, no.~03, pp. 1182--1188, 2016.

13. R. Weeraskera, K. F. Chang, S. Zhang., G. Katti., H. Y. Li, R. Dutta and J. R. Cubillo., "High Bandwidth Interconnect Design Opportunities in 2.5D Through-Silicon Interposer (TSI)", in Proc. IEEE Electronics Packaging Technology Conference (EPTC), 2016

14.  X.  Zhang, J-K. Lin, S. Wickramanayaka, S.  Zhang, R. Weerasekera, R. Dutta, K. F. Chang, K.-J. Chui, H. Y. Li, D. S. W. Ho, L. Ding, G. Katti, S. Bhattacharya, and D.-L. Kwong, "Heterogeneous 2.5D Integration on Through Silicon Interposer", Invited Paper, Applied Physics Reviews, vol.~02, no.~02,  021308, 2015.

15.  G. Katti, S.W. Ho, L. H.Yu, Z. Songbai, R. Dutta, R. Weerasekera, C.K. Fai, Jong-Kai Lin, S.R. Vempati, S. Bhattacharya, "Fabrication and Assembly of Cu-RDL based 2.5D Low Cost Through Silicon Interposer (LC-TSI)", in IEEE Design & Test,  vol.~32, no.~04, pp. 23--31, 2015.

16.  C. Wang, J. Zhou, R. Weerasekera, B. Zhao,  X. Liu, P. Royannez, and J. Minkyu, "BIST Methodology, and Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems", in IEEE Transactions on Circuits and Systems I, vol.62, no.1, pp.139,148, Jan. 2015 

17.  C. F. Chang,R. Weeraskera and S. Bhattacharya, "Electrical transmission characteristics of vertical transition with through silicon vias (TSVs) in 3D die stack", In Proc. IEEE Electronics Packaging Technology Conference (EPTC), 2015

18.  S. Ma, J. Ren, P. D. Sai Manoj, H. Yu and R. Weeraskera, "A 9.8 Gbps, 6.5 mW Forwarded-clock Receiver with Phase Interpolator and Equalized Current Sampler in 65 nm CMOS", in Proc. IEEE International Microwave Symposium (IMS), May 2015, pp.1-4  (Student Paper Competition Finalist)

19.  G. Katti, Y. Weiliang, R. Weerasekera, K. F. Chang,R. Dutta, H. Y. Li, D. H. S. Wee and S. Bhattacharya,"Monolithic Integration of High Capacitance (Power/Ground) and Low Capacitance (Data) Through Silicon Vias (TSV) in 2.5D Through SiliconInterposer (TSI) and 3D IC Technology", in Proc. IEEE international conference on Electron Devices and Solid State Circuits (EDSSC), 2015, pp. 249 - 252

20.  C. Wang, J. Zhou, G. Katti, X. Liu, R. Weerasekera and Tony T. Kim,"TSV-Based PUF Circuit for 3DIC Sensor Nodes in IoT Applications", in Proc. IEEE international conference on Electron Devices and Solid State Circuits (EDSSC), 2015, pp. 313 - 316

21.  R. Weerasekera, Z. Songbai, R. Dutta, G. Katti, K. F. Chang, J. Zhou, J.-K. Lin and S. Bhattacharya,"Heterogeneous System Implementation Using Through-Silicon Interposer(TSI) Technology", in Proc. IEEE international conference on Electron Devices and Solid State Circuits (EDSSC), 2015, pp.391-394

22.  S. Zhang, K. F. Chang, C. Jin, G. Katti, R. Weerasekera, and S. Bhattacharya, "60GHz wideband Yagi-Uda antenna integrated on 2.5D through silicon interposer," In Proc. Electronics Packaging Technology Conference (EPTC), 2014, pp. 665-668.

23.  J. Wang, S. Ma, Sai Manoj P. D., M. Yu, R. Weerasekera, H. Yu, "High-Speed and Low-Power 2.5D I/O Circuits for Memory-logic-integration by Through-Silicon Interposer",  IEEE International 3D System Integration Conference (3DIC), October 2013. (to appear)

24.  C. C. Wong, C. Drews,Y. Chen, T. S. Pui, S. K. Arya, R. Weerasekera, and A. R. A. Rahman, "CMOS based High Density Micro Array Platform for Electrochemical Detection and Enumeration of Cells", in Proc. IEEE International Electron Devices Meeting (IEDM), 2013, pp. 14.2.1 - 14.2.4

25.  S. Hu, J. Shi, K. H. Teo, R. Weerasekera and   Y. Z. Xiong, "Nanoscale CMOS Transistors at Variable Temperature for Low-voltage Millimeter-wave Circuits", In Proc. MRS Internation Conf. on Materials for Advanced Technologies, 2013

26.  T. S. Pui, C. Yu, C. C. Wong, R. Nadipalli, R. Weerasekera, H. Yu, and A. R. A. Rahman, "High Density CMOS Electrode Array for High-throughput and Automated Cell Counting", Elsevier Sensors and Actuators B: Chemical, vol.181, pp. 842-849, May 2013.

27.  R. Weerasekera, H. Y. Li, L. W. Yei, H. Sanming, J. Shi, J. Minkyu and K. H. Teo,  "On the effect of Through-Silicon Via (TSV) Induced Stress on 65 nm CMOS Devices" In IEEE Electron Device Letters, vol. 34, no. 1, pp. 18-20, Jan, 2013.

28.  Y. Chen, C. C. Wong., T. S. Pui., R. Nadipalli, R. Weerasekera, J. Chandran, H. Yu, and A. R. A. Rahman, "CMOS High Density Electrical Impedance Biosensor Array for Tumor Cell Detection", Elsevier Journal of sensors and actuators: Chemical, Elsevier Sensors and Actuators B: Chemical, vol.173, pp. 903-907, October 2012

29.  A. Y. Weldezion, R. Weerasekera and H. Tenhunen, "Design Space Exploration of Clock-pumping Techniques to Reduce Through Silicon Via (TSV) Manufacturing Cost In 3-D Integration", In Proc. IEEE Electronics Packaging Technology Conference (EPTC), 2012, pp. 19 - 22

30.  J.R. Cubillo, R. Weerasekera and G. Katti, "Through-Silicon Interposer (TSI) co-design optimization for high performance systems", In Proc. IEEE Electronics Packaging Technology Conference (EPTC), 2012, pp. 93- 98. 

31.  R. Weerasekera, J.R. Cubillo, and G. Katti, "Analysis of Signal Integrity Robustness over TSI Interconnects", In Proc. IEEE Electronics Packaging Technology Conference (EPTC), 2012, pp. 397 - 398

32.  Yuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu and R. Weerasekera, "Design Exploration of 3D Stacked Non-Volatile Memory by Conductive Bridge based Crossbar", in Proc. IEEE International Conference on 3D System Integration (3D IC), 2012.

33.  J.R. Cubillo, R. Weerasekera, Z.Z. Oo, E-X. Liu, B. Conn, S. Bhattacharya, and R. Patti," Interconnect Design and Analysis for Through Silicon Interposers (TSIs)" in Proc. IEEE International Conference on 3D System Integration (3D IC), 2012. 

34.  A. C. Fischer, M. Grange, N. Roxhed, R. Weerasekera, D. Pamunuwa, G. Stemme,  and F. Niklaus. "Wire-bonded through-silicon vias with low capacitive substrate coupling", Journal of Micromechanics and Microengineering, 21, (pp. 085035-), 2011

35.  M. Grange, A. Jantsch, R. Weerasekera, and D. Pamunuwa, "The Computational Efficiency of 2-D and 3-D Silicon Processors for Early-Chip Planning", in Proc. IEEE/ACM International Conference on Computer-Aided Design, November, 2011, pp. 310-317.

36.  M. Grange, R. Weerasekera, D. Pamunuwa, A. Jantsch, A. Y. Weldezion, "Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks", in Proc. International Symposium on Networks-On-Chip (NoCS), PA, USA, 2011, pp. 57-64. 

37.  R. Weerasekera, M. Grange, D. Pamunuwa, and H. Tenhunen, "On Signalling over Through-Silicon Vias (TSVs) in Three-Dimensional ICs", in Proc. Design, Automation and Test in Europe (DATE), 2010, pp. 1325-1328.

38.  W. Ahmad, L.-R. Zheng, R. Weerasekera, Qiang Chen, Awet Yemane Weldezion, H. Tenhunen, "Power Integrity Optimization of 3D Chips Stacked Through TSVs", in Proceedings of the Topical Meeting on Electrical Performance of Electronic Packaging and Systems, October, 2009, pp. 105-108.

39.  A. Y. Weldezion, Z. Lu, R. Weerasekera, and H. Tenhunen, "3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture" in Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 2009

40.  M. Grange, A. Y. Weldezion, D. Pamunuwa, R. Weerasekera, H. Tenhunen and D. Shippen, "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh". In Proc. IEEE International Conference on 3D System Integration, San Francisco - USA, September 2009.

41.  R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L-R. Zheng, "Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuit", in Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 2009.

42.  R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints," In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1237-1250, Aug 2009.

43.  A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, and H. Tenhunen, "Scalability of network-on-chip communication architecture for 3-d meshes", In Proc. the International Symposium on Networks-on-Chip, San Diego, CA, May 2009.

44.  R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, and L.-R. Zheng, "Closed-Form Equations for Through-Silicon Via Parasitics in 3D ICs" 3D Integration workshop, DATE 2009

45.  M. Grange, R. Weerasekera, D. Pamunuwa and H. Tenhunen, "Examination of Delay and Signal Integrity Metrics in TSVs", 3D Integration workshop, DATE 2009

46.  W. Ahamd, Q. Chen, R. Weerasekera, H. Tenhunen and L.-R. Zheng, "Power Integrity Issues in 3D ICs using TSVs", 3D Integration workshop, DATE 2009

47.  A. Y. Weldezion, R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Bandwidth Optimization for Through Silicon Via Bundles in 3D ICs" 3D Integration workshop, DATE 2009

48. R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime," In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 589-593, May, 2008. 

49. B. Shao, R. Weerasekera, A. T. Woldegiorgis, L.-R. Zheng, R. Liu, and W. Zapka, "High Frequency Characterization and Modeling of Inkjet Printed Coplanar Strips on Flexible Substrate", in Proceedings of the 2nd Electronics System-Integration Technology Conference, London, UK, September, 2008, pp. 695-699.

50.  B. Shao, R. Weerasekera, L.-R. Zheng, R. Liu, W. Zapka, and P. Lindberg, "High Frequency Characterization of Inkjet Printed Coplanar Waveguides", 12th IEEE Workshop on Signal Propagation on Interconnects, May, 2008, pp.1-4.

51.  R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs," in Proc. IEEE/ACM international conference on Computer-aided design, IEEE Press, November, 2007, pp. 212-219.

52.  R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Early selection of system implementation choice among SoC, SoP and 3-D Integration", In Proc. IEEE International System-on-Chip Conference, September, 2007, pp.187-190.

53.  B. Shao, R. Weerasekera, A. T. Woldegiorgis, L.-R. Zheng, Ran Liu, W. Zapka, and P. Lindberg, "Electrical Characterization of Inkjet Printed Interconnections on Flexible Substrates", IEEE CPMT Symposium on Green Electronics, Goteborg, Sweden, 2007.

54.  R. Weerasekera, A. T. Woldegiorgis, B. Shao, S. R. Duenas, L.-R. Zheng, P. Lindberg, W. Zapka, and H. Tenhunen, "Electrical Characterization of Ink-Jet Printed Interconnects on Plastic for Low-Cost RFID", IEEE International Conference on Industrial and Information Systems, Peradeniya, Sri Lanka, 2007.

55.  R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Delay-Balanced Smart-Repeaters for on-chip Global Signaling", In Proc. International Conference on VLSI Design, 2007, pp. 308-313.

56.  Jian Liu, R. Weerasekera, L.-R. Zheng, and H. Tenhunen, "Exploration of Autonomous Error-Tolerant (AET) Celluar Networks in System-on- a Package (SoP) for Future Nanoscale Electronic Systems", IEEE International Conference on Industrial and Information Systems, Peradeniya, Sri Lanka, 2006.

57.  D. Pamunuwa and R. Weerasekera, "Nanoelectronics: from novelty toys to functional Devices - an integration perspective", IEEE International Conference on Industrial and Information Systems, Peradeniya, Sri Lanka, 2006, Invited Paper.

58.  R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Minimum-Power, Delay-Balanced Drivers for interconnects in the Nanometer Regime", in Procs. International workshop on System-Level interconnect prediction, German, March, 2006, pp. 113-120.

59.  R. Weerasekera, L.-R. Zheng, D. Pamunuwa and H. Tenhunen, "Switching sensitive interconnect Driver to Combat Dynamic Delay in on-Chip Buses" in the Lecture Notes in Computer Science 3728 Edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest, Springer 2005, ISBN 3-540-29013-3, pp. 277-285

60.  R. Weerasekera, Jian Liu, L.-R. Zheng, and H. Tenhunen, "A Nanocore/ CMOS Hybrid System-on-Package (SoP) Architecture for Future Nano-electronic Systems", In Proc. High Density Microsystem Design and Packaging and Component Failure Analysis Conference, June, 2005, pp.1-4.

61.  Jian Liu, R. Weerasekera, L.-R. Zheng, and H. Tenhunen. "Nanocore/ CMOS hybrid system-on-package(sop) architecture for autonomous error-tolerant (aet) cellular array network", in Proc. IEEE Conference on Nanotechnology, Nagoya, Japan, 2005.

62.  Jian Liu, R. Weerasekera, L.-R. Zheng, and H. Tenhunen, "Nano scale autonomous error-tolerant (aet) cellular network", in Proc. Nanotechnology Conference and Trade Show, California, USA, May, 2005, pp. 748-751.

63.  R. Weerasekera, Jian Liu, L.-R. Zheng, and H. Tenhunen. "A nanocore/cmos hybrid system-on-package (sop) architecture for future nano-electronic systems", in Proc. Nanotechnology Conference and Trade Show, California, USA, May, 2005, pp. 157-160.

64.  R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "Crosstalk Immune Interconnect Driver Design", in Proc. International Symposium System-on-Chip, November, 2004, pp. 139 - 142.