List of Publications

Refereed Journal

1.  Siddhartha Sarma, Rahul Shrestha and Rohit B. Chaurasiya, “Energy-preserving Indirect-feedback for Wireless Power Transfer: Algorithm & Hardware Architecture,” IEEE Transactions on Green Communications and Networking, Early Access, March-2025, Click here to Access the Paper

2. Rohit B. Chaurasiya and Rahul Shrestha, “Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion Based Cognitive Radio Network,” IEEE Transactions on Consumer Electronics, Volume: 68, Issue: 3, pp. 221-235, August-2022. Click here to Access the Paper 

3. Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient VLSI-Architecture and ASIC-Implementation of GRCR based Cooperative Spectrum Sensor for Cognitive-Radio Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 30, Issue: 2, pp. 166-176, February-2022.  Click here to Access the Paper

4.  Rohit B. Chaurasiya and Rahul Shrestha, “Area-Efficient and Scalable Data-Fusion based Cooperative Spectrum Sensor for Cognitive Radio,” IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 68, Issue: 4, pp. 1198-1202, April-2021.  Click here to Access the Paper

5.  Rohit B. Chaurasiya and Rahul Shrestha, “A New Hardware-Efficient Spectrum-Sensor VLSI-Architecture for Data Fusion based Cooperative Cognitive-Radio Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 29, Issue: 4, pp. 760-773, February-2021. Click here to Access the Paper 

6.  Rohit B. Chaurasiya and Rahul Shrestha, “Fast Sensing-Time and Hardware-Efficient Eigenvalue based Blind Spectrum Sensors for Cognitive Radio Network,”  IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 67, Issue: 4, pp. 1296-1308, April-2020. Click here to Access the Paper

7.  Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue based Spectrum Sensor for Cognitive Radio Network,”  IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 66, Issue: 11, pp. 4448-4461, November-2019. Click here to Access the Paper 

8.  Divya K. Shah, Rohit B. Chaurasiya, Vishwesh A. Vyawahare, Khushboo Pichhode, Mukesh D. Patil, “FPGA implementation of fractional-order chaotic systems,” AEU - International Journal of Electronics and Communications, Volume: 78, pp. 245-257, August-2017.  Click here to Access the Paper

Peer-Reviewed Conference

1. Mansi Shukla, Anand Singh Thakur, Rohit Chaurasiya and Deepika Gupta, “FPGA Implementation of Resource-Efficient Cube Calculation Architecture using Yavadunam Sutra,” 27th International Symposium on VLSI Design and Test (VDAT-2023), In Press, September-2023, BITS-Pilani, Pilani (India). {In Press}

2.  Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network,”  IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May-2021, South Korea (Daegu). Click here to Access the Paper 

3.  Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED based Spectrum Sensor for Cognitive Radio,”  IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May-2019, Japan (Sapporo). Click here to Access the Paper

4.  Rohit Chaurasiya, John Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers, “Parameterized Posit Arithmetic Hardware Generator,” 36th IEEE International Conference on Computer Design (ICCD), pp. 334-341, October-2018, USA (Orlando, Florida). Click here to Access the Paper

5.  Khushboo Pichhode, M. D. Patil, Divya Shah and Chaurasiya Rohit B, “FPGA implementation of efficient vedic multiplier,” IEEE International Conference on Information Processing (ICIP), pp. 565-570, December-2015, India (Pune). Click here to Access the Paper

6.  Divya Shah, Chaurasiya Rohit B, Devdip Sen and Shaswat Goyal , “Vehicle parking system implementation using CPLD,” IEEE International Conference on Communication, Information & Computing Technology (ICCICT), pp. 1-5, January-2015, India (Mumbai). Click here to Access the Paper

7.  Chaurasiya Rohit B.,M. D. Patil,Divya Shah and Abhijit Kadam , “FPGA implementation of SVPWM control technique for three phase induction motor drive using fixed point realization,” IEEE International Conference on Circuits, Systems, Communication and Information Technology Applications (CSCITA), pp. 93-98, April-2014, India (Mumbai). Click here to Access the Paper