AIDASoft

The Analog IC Design Automation (AIDASoft) framework implements an analog IC design flow a from circuit-level specification to a physical layout description focusing on design optimizing and porting using highly efficient searching methods combined with accurate circuit-level simulation engines.

AIDASoft was developed at Instituto de Telecomunicações by Nuno Horta, Nuno Lourenço and Ricardo Martins.

Some of the Related Publications:

L. Mendes et al., "Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications," in IEEE Transactions on Microwave Theory and Techniques, vol. 73, no. 8, pp. 4828-4841, Aug. 2025, doi: https://10.1109/TMTT.2025.3537588
A. Canelas et al., "Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs," in IEEE Access, vol. 9, pp. 124152-124164, 2021, doi: https://10.1109/ACCESS.2021.3110758
L. Mendes, J. C. Vaz, F. Passos, N. Lourenço and R. Martins, "In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization," in IEEE Access, vol. 9, pp. 70353-70368, 2021, doi: https://10.1109/ACCESS.2021.3078240
R. Martins et al., "Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3965-3977, Nov. 2020, doi: https://10.1109/TCSI.2020.3009857
F. Passos et al., "Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology," in IEEE Access, vol. 8, pp. 51601-51609, 2020, doi: https://10.1109/ACCESS.2020.2980211
N. Lourenço, R. Martins, A. Canelas, R. Póvoa and N. Horta, "AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation," Integration, the VLSI, vol. 55, pp. 316-329, Sept. 2016. doi: https://doi.org/10.1016/j.vlsi.2016.04.009

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