Belief propagation at scale for real-time decoding 

Abstract 

TBC

Quantum LDPC Codes in Practice with Trapped-Ions

Affiliation

Staff Engineer, IonQ

Abstract

Quantum Low-Density Parity-Check (qLDPC) codes can encode dramatically more logical qubits, in the same physical footprint and at comparable logical error-rates, as their 2D topological counterparts like the surface code. Still, their real-world implementation has proven difficult for a variety of reasons, ranging from non-trivial two-qubit gate connectivity requirements to challenging decoder design. We report on a demonstration of multiple high-rate qLDPC code instances on a 40-qubit trapped-ion device. Our demonstration achieves up to 9x better logical error-rates than a comparable implementation on solid-state superconducting qubits and exhibits logical qubit lifetimes in the breakeven regime.

Talk Abstract : TBC

Scalable system design toward FPGA-based quantum error correction with superconducting qubits

Affiliation

Principal, Processor Research Team

Leader, Advanced AI Device Development Unit (AI for Science Platform Division)

Leader, Next-Generation HPC Infrastructure System Development Unit (Next-Generation HPC Infrastructure Development Division)

RIKEN Center for Computational Science (R-CCS)

Abstract

For quantum error correction (QEC) of logical qubits, it is necessary to perform error decoding that estimates most-likely errors of physical qubits and measurement based on the syndrome information obtained with ancillary qubits. Since we need to solve a minimum-weight perfect matching (MWPM) problem for error decoding within microsecond-order latency in the case of superconducting qubits, a scalable algorithm and its parallel hardware implementation are required especially for high distance error-correction codes. In this talk, we introduce our research project on QEC as the JST Moonshot Goal 6 project, where we develop an error correction algorithm for a surface code on superconducting qubits and an FPGA-based system for QEC experiments that allows scalable and low-latency execution of the algorithm.

Bio

Kentaro Sano is the principal of the processor research team, and the leaders of the advanced AI device development unit and the next-generation high-performance computing infrastructure system development unit at RIKEN Center for Computational Science (R-CCS), responsible for research and development of future processors and systems for HPC and AI. He is also a visiting professor with an advanced computing system laboratory at Tohoku University. He received his Ph.D. from Tohoku University in 2000. His research interests include CGRAs, FPGA-based high-performance reconfigurable computing, quantum error correction hardware for fault-tolerant quantum computers, and next-generation supercomputer architectures including FugakuNEXT.

Shor’s algorithm is possible with as few as 10,000 reconfigurable atomic qubits

Abstract: Quantum computers have the potential to perform computational tasks beyond the reach of classical machines. A prominent example is Shor’s algorithm for integer factorization and discrete logarithms, which is of both fundamental importance and practical relevance to cryptography. However, due to the high overhead of quantum error correction, optimized resource estimates for cryptographically relevant instances of Shor’s algorithm require millions of physical qubits. Here, by leveraging advances in high-rate quantum error-correcting codes, efficient logical instruction sets, and circuit design, we show that Shor’s algorithm can be executed at cryptographically relevant scales with as few as 10,000 reconfigurable atomic qubits. Increasing the number of physical qubits improves time efficiency by enabling greater parallelism; under plausible assumptions, the runtime for discrete logarithms on the P-256 elliptic curve could be just a few days for a system with 26,000 physical qubits, while the runtime for factoring RSA-2048 integers is one to two orders of magnitude longer. Recent neutral-atom experiments have demonstrated universal fault-tolerant operations below the error-correction threshold, computation on arrays of hundreds of qubits, and trapping arrays with more than 6,000 highly coherent qubits. Although substantial engineering challenges remain, our theoretical analysis indicates that an appropriately designed neutral-atom architecture could support quantum computation at cryptographically relevant scales. More broadly, these results highlight the capability of neutral atoms for fault-tolerant quantum computing with wide-ranging scientific and technological applications.

From Decoders to Integrated Systems: Generator-Based Agile QEC System Development

Abstract 

TBC

Real-time quantum error correction requires decoding with control flow awareness 

Abstract 

TBC