CPE 487

https://github.com/romanbell/dsd
https://www.linkedin.com/in/romanbellisari/

Week 1

• • Created Google website with a link to my GitHub page

  • Familiarized myself with the Free Range VHDL textbook

Week 2

• • Downloaded Vivado at home using the references listed on the course google site

  • Read chapter 3 and 4 in Free Range VHDL textbook

  • Looked into the syntax and naming systems of VHDL

  • Attempted to learn how to translate black box diagrams into VHDL entity declarations (and vice versa)

  • Learned about topics linked to the ECE 487 page such as Endianness and Bit Numbering

Week 3

• • Reviewed the upcoming procedure moving forward with the new boards, how to run the GitHub code and how to set up Vivado

  • Discussed main topics in chapter 5

    • Data flow style Architecture (More straightforward)

    • Behavioral Architecture (More complex)

  • Went through main topics in chapter 6

  • Nexys A7 Setup along with Vivado software setup (how to use Nexys A7 with Vivado)

Week 4

• • Reviewed chapter 7 in the VHDL text book

  • Re-downloaded the correct board file for the Nexys A7

  • Followed along the lab 1 manual, completing each step as follows

  • Finished the first lab with the result being the ability to manipulate the switches for the digital numbers to appear on the board

    • See more lab info here

  • Reviewed chapter 8 and finite state machine design

    • Referenced stop lights and the complexities of modern city planning and traffic system design

Week 5

• • (No class Tuesday)

  • Began lab 2 by following instructions on the E487 GitHub Page

Week 6

• • Reviewed some concepts from chapter 10 from the textbook

  • Discussed global supply chain processes and its relationship with DSD

    • Importance of FPGA (many large finance companies looking for FPGA)

  • Completed lab 2 up to the last step (error with "Add memory configuration device" in Vivado)

  • Reviewed topics from chapter 11 from the textbook

Week 7

• • No class Tues - Thurs

Week 8

• • No class Tue, Zoom meeting on thursday

  • Discussed chapter 12 in the Free Range VHDL textbook

  • Compared GHDL to other programs such as Vivado and the installation processes involved

  • Discussed logistics moving forward with Zoom meetings

  • Introduced the final project guidelines and how to get started

  • Researched into past projects from Cornell's VHDL course

Week 9 (Zoom Lecture)

• • Talked about how to run Vivado without a FPGA board

  • Learned about potential alternatives for obtaining a board while off campus through a reimbursement and school discount

  • Followed the instructions on how to add views to a Google website using Google Analytics

  • Learned helpful organizational techniques in GitHub

Week 10 (Zoom Lecture)

• • Researched into GHDL and how to develop a final project without a physical board

  • Downloaded GHDL from here

  • Updated my GitHub to include a DSD repository

  • Reviewed final projects from previous years for inspiration

Week 11 (Zoom Lecture)

• • Found a cool FPGA project from University of Illinois on YouTube, digital synthesizer project

  • Also this guy created a cool low pass filter using Verilog

  • Learned about 3D printed face masks and the relationship between COVID-19 and FPGA

  • Downloaded and installed GTKWave

  • Researched into audio synthesizer design process for a final project idea.

Week 12 (Zoom Lecture)

• • Continued research into my digital/analog synthesizer report

Week 13 (Zoom Lecture)

• • Focusing on working on labs

  • Continue final project research

Week 14 (Final Zoom Lecture)

• • Website is not entirely complete/ready for review

    • Still working on completing lab 6, finalizing project and updating GitHub repo