Journals

  1. Sachin Maddheshiya, Ramanuj Chouksey and Chandan Karfa, “VP_TT: A Value Propagation Based Equivalence Checker for Testability Transformations,” IET Software, 2020

  2. Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. Verification of scheduling of conditional behaviors in high-level synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), pages 1-14, Mar 2020.

  3. Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. Translation validation of code motion transformations involving loops. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 38(7):1378–1382, Jul 2019.

  4. Ramanuj Chouksey, Chandan Karfa, Kunal Banerjeeand Pankaj Kumar Kalita, and Purandar Bhaduri. Counter-example generation procedure for path-based equivalence checkers. IET Software, 13(4):280–285, Aug 2019.

Conferences

  1. Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey and Ramesh Karri, “HOST: HLS Obfuscations against SMT ATtack,” in 23rd Conference on Design, Automation and Test in Europe (DATE'21), pp. -, March 2021.

  2. Melbin John, Aadil Hoda, Ramanuj Chouksey and Chandan Karfa, “SAT Based Partial Attack on Compound Logic Locking,” in IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), December 2020.

  3. Pankaj Kalita, Ramanuj Chouksey and Chandan Karfa, “Automatic Inverse Operation Detection and its Impact in High-level Synthesis,” in 24th International Symposium on VLSI Design and Test (VDAT 2020), pp. 1-4, August 2020

  4. Chandan Karfa and Ramanuj Chouksey and Christian Pilato and Siddharth Garg and Ramesh Karri. Is Register Transfer Level Locking Secure?, Design, Automation, and Test in Europe (DATE 2020), 2020.

  5. Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. Improving performance of a path-based equivalence checker using counter-examples. In International Conference on VLSI Design (VLSID), pages 377–382, Jan 2019.

  6. Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. Formal verification of optimizing transformations during high-level synthesis. In Innovations on Software Engineering Conference, ISEC’19, pages 27:1–27:5, Feb 2019.

  7. Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa and Pankaj Kumar Kalita, “Poster: Automatic detection of inverse operations while avoiding loop unrolling,” in ICSE, 2018, pp. 175–176.

  8. Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. Translation validation of loop invariant code optimizations involving false computations. In VLSI Design and Test (VDAT), pages 767–778, Dec 2017.