Rahul bera
Rahul bera
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Senior Researcher | Huawei Zürich Research Center
Senior Researcher | Huawei Zürich Research Center
<firstname> dot <lastname> at huawei dot com
I am currently employed as a Senior Researcher at Huawei Zürich Research Center, working on disaggregated memory system design. I earned my Ph.D. from ETH Zürich in 2026, where I was advised by Prof. Onur Mutlu. Previously, I have worked in various capacities at Intel Labs (under the mentorship of Anant V. Nori and Sreenivas Subramoney) and AMD. I'm interested in the broad area of memory hierarchy design and energy-efficient architectures.
Experience
Experience
- Senior Researcher, Huawei Zürich Research Center, Switzerland [Mar 2026 - Present]
- Graduate Research Intern, Intel Processor Architecture Research Lab, India [Mar - Aug 2023]
Instruction elimination opportunities for power-efficient microarchitecture design
Mentors: Anant V. Nori and Sree Subramoney
- Architecture Researcher, Intel Processor Architecture Research Lab, India [Feb 2017 - Aug 2019]
Aggressive prefetcher design and optimization for next generation processor
Near-cache computing for efficient DNN inference in CPU
Mentors: Anant V. Nori and Sree Subramoney
- Co-op Engineer, Server SoC Perf Team, AMD India, Bangalore [July - Dec 2015]
Designing a simulation framework alternative to instruction-based tracing for to evaluate extrmely-threaded workloads
Mentor: Dr. Kanishka Lahiri
Education
Education
- Doctor of Philosophy [Sept 2019 - Dec 2025]
- Master of Technology in Computer Science [July 2014 - Jan 2017]
- Bachelor of Enginnering in Computer Science [July 2010 - April 2014]
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