Schedule
15 SEP 2026

We present a tensor-network-based digital twin for quantum computers, designed to simulate large-scale quantum systems in the presence of noise and hardware imperfections. The framework can be integrated with quantum compilation and optimal-control techniques for quantum-gate pulse design. We apply the approach to neutral-atom quantum computers and benchmark the preparation of a 64 qubits GHZ state in three-level atoms under realistic error sources, including crosstalk between parallel two-qubit gates. During the journey, we present recent developments in quantum optimal control, tensor networks and quantum compilation. 

Scalable quantum computers will not emerge by optimizing devices, control, compilation, and architecture in isolation. They require an engineering cycle in which physical constraints, computational workloads, and architectural decisions continuously inform one another. This talk illustrates how we approach this co-design problem across three layers of the quantum stack. At the control layer, we discuss energy-aware quantum optimal control, where gate fidelity and energetic cost define a Pareto trade-off and motivate both open- and closed-loop pulse optimization. At the instruction-set layer, we show how native gate selection can be formulated as workload-conditioned design-space exploration which balances circuit depth, approximation fidelity, and gate-set novelty. At the architecture layer, we examine how connectivity, crosstalk, compilation, and qubit movement jointly determine system performance. This motivates recent work on deep-reinforcement-learning-based state shuttling in semiconductor quantum-dot arrays, where policies trained on ideal systems generalize to unseen noise and longer device chains.

As quantum computing matures, the central challenge is no longer only improving individual devices, but making quantum systems usable within larger hybrid computing workflows.

In this talk, we present recent progress at Pasqal towards full-stack neutral-atom quantum computing, with the engineering-cycle perspective suggested by the workshop. We discuss how software and systems layers help translate hardware capabilities into usable computational resources. Particular emphasis will be placed on the interfaces between device constraints and higher-level execution: how noise, calibration overhead, control limitations, and application requirements shape the design and deployment of practical quantum workflows.

We illustrate this approach through recent hardware and application advances: the use of 256 qubits for quantum simulation of a real material, and the demonstration of an end-to-end logical quantum algorithm deployed on a neutral-atom QPU. These examples highlight how in-depth analysis of algorithm requirements and performance informed hardware development, and vice versa.

Together, they support a methodology in which modelling, control, software, and application performance are tightly and scalably integrated.

Megaquop-capable, early fault-tolerant machines are coming online, bringing a rapid expansion of experimentation with computing use cases involving a few hundred imperfect logical qubits. As co-design becomes a game constrained by fault-tolerance requirements, these platforms make heuristic approaches to quantum optimization and quantum machine learning, rather than more sophisticated algorithms promising clear advantage, natural targets for early application development.

Multiple examples of this hardware are expected to offer low-level control, including mid-circuit measurement, feed-forward, and dynamic-circuit capabilities. These features will enable new paradigms for setting algorithmic parameters and controlling quantum devices. In many state-of-the-art application demonstrations, we face a choice between offline strategies (in which parameters are fixed in advance using reduced models, classical surrogates, or knowledge transferred from smaller instances) and online, closed-loop tuning directly against the hardware. We will discuss with examples how application performance and hardware benchmarking are evolving in response to these new quantum-engineering capabilities.

Quantum algorithms have long been designed in the abstract — assuming perfect gates, idealized error models, and hardware that doesn't yet exist. That gap is closing, but not just because hardware is improving. The real shift is that the systems layer is finally catching up: AI-driven calibration is delivering cleaner, more characterizable qubits; real-time decoders are making error correction practically viable; and ultra-low-latency quantum–classical links are enabling the hybrid feedback loops that the most promising near-term algorithms demand. This talk examines what that means for algorithm design and discovery.

Accelerated emulation is compressing the iteration cycle, letting us probe algorithmic behavior at scales and noise regimes previously out of reach. Higher-fidelity, better-characterized hardware is expanding the class of circuits worth designing for. And tighter quantum–classical integration is opening the door to variational, adaptive, and fault-tolerant algorithms that require real-time classical co-processing at scale. Rather than waiting for hardware to mature, the emerging blueprint of an accelerated quantum supercomputer gives algorithm designers a concrete, near-term target — one where co-design between the algorithmic and systems layers is the fastest route to demonstrating genuine quantum advantage.

TBC