Phase 1
High level synthesis HLS also known as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis.
Synthesis begins with high level description of the problem, code is translated into RTL design in HDL, which is then converted to gate level by using logic synthesis tool.
Finite State Machines:
Process stages[edit]
Process stages[edit]
he high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.[10]
- Lexical processing
- Algorithm optimization
- Control/Dataflow analysis
- Library processing
- Resource allocation
- Scheduling
- Functional unit binding
- Register binding
- Output processing
- Input Rebundling
Products Available in the market:
- https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html
- https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
- https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html
- http://kastner.ucsd.edu/ryan/vivado-installation/
FPGA Architecture: