Storytelling 

I am a master's student at the University of Colorado Boulder with a specialisation in Power Electronics. With my interest in Power Electronics and Analog, I always want to implement my classroom learning in the workplace and TI has given me this opportunity. During my time at TI, I grew both personally and professionally.  I worked in the BMP(Battery Monitor Product) group in the BMS group. I feel fortunate to work with professional experts in this domain who shaped my idea and gave the correct direction to solve the real-time challenge, During my time at TI I worked on real-time projects of BQ79718 and BQ79826.

 Questioning is the Beginning of real intelligence 

Technical Skills learnt: Cadence, Simvision, Gfarm, Unix, Test case flow and base test case understanding, Verilog_Ams(Basic)

Task_01 (BQ79718)

Problem Statement: ON the OW sims of different pins and cell voltages, after reviewing the waveform, We can see that the 120ms default time for the OW detection is too much. There is a quite difference in the time it actually takes for the open pin to settle. My task is to write the code to adjust the wait time for each of the 10OW jobs.

Outcomes and learning: I implemented the code using the system Verilog and ran all 10 jobs, after successfully completing the simulation. We got significant time savings from the previous result. Earlier it was taking 409hr but now all the same jobs can be done in 266 hr, which is approx 50% time-saving. 

Task_02 (BQ79718)

Problem Statement: Speed up the power mode (wake, sleep, active) by removing unnecessary circuits out of the configuration, and measure the time saved after taking this circuit out of the configuration.

Outcomes and Learning: I removed some circuits from the configuration and saved approximately 10 of the sim time during the power state.

Task_03(BQ79718)

Problem Statement: How to Add a new feature for all our upcoming ICs to detect the fault in AVDD and DVDD during sleep mode.

Outcomes and Learning: I have implemented the Verilog code and run the complete test case, It has passed all the designed criteria and we can use this new feature for all our upcoming IC family.

Task_04(BQ79826)

Problem Statement: Write the send_data tone to drive the VIF2_Rx to check the tone detector

Outcomes and Learning: I have written the Verilog_AMS code and checked the wake, wake_os, and HWRST signals to validate the working of the tone detector. I have sent finite and random 1000 bits of data between NCS_0 and NCS_1.  

Task_05(BQ79826)

Problem: Run the test case for ADC, OW and GPIO and find the errors and bugs in the design

Outcomes and Learning: I have performed all the sims and reported the error in the OW test case to the designer. 

I am so grateful for the investment TI has made in me as a professional and an individual. Special thanks to my mentor, Supervisor and the BMS team for helping me during my internship.