Publications
Journal Papers
Yung-Chih Chen, Li-Cheng Zheng, and Hao-Ju Chang, 2023, 9, "Don’t-Care-Based Logic Optimization for Threshold Logic", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 9, pp. 2980-2993.
Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, 2022, 11, "A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 41, no. 11, pp. 4821-4825.
Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, and Chun-Yao Wang, 2022, 5, "Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1412-1422.
Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, 2022, 3, "Majority Logic Circuit Minimization Using Node Addition and Removal," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3. pp. 642-655.
Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, 2022, 1, "LOOPLock 2.0 : An Enhanced Cyclic Logic Locking Approach," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, No. 1, pp. 29-34.
Yi-Wen Hung, Yung-Chih Chen, Chi Lo, and Shih-Chieh Chang, 2021, 3, "Dynamic Workload Allocation for Edge Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 3, pp. 519-529.
Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, and Chun-Yao Wang, 2021, 1, "Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 17, no. 2, article 15.
Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, and Chun-Yao Wang, 2020, 12, "A New Necessary Condition for Threshold Function Identification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 5304-5308.
Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, and Chun-Yao Wang, 2020, 10, "LOOPLock: LOgic OPtimization based Cyclic Logic Locking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 2178-2191.
Yung-Chih Chen, 2020, 5, "SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E103.A(5).
Yung-Chih Chen, Li-Cheng Zheng, and Fu-Lian Wong, 2019, 11, "Optimization of Threshold Logic Networks with Node Merging and Wire Replacement," ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 6, article 67.
Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, and Shigeru Yamashita, 2019, 12, "Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 12, pp. 2284-2297.
Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, and Shih-Chieh Chang, 2018, 6, "Contactless Testing for Prebond Interposers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 6, pp. 1005-1014.
Yung-Chih Chen, 2018, 7, "Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption," ACM Transactions on Design Automation of Electronic Systems, vol. 23, no. 4, article 52.
Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, and Chun-Yao Wang, 2018, 12, "On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2842-2852.
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, and Vijaykrishnan Narayanan, 2017, April, "Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays," IEEE Transactions on VLSI Systems (TVLSI), vol. 25, no. 4, pp. 1477-1489.
Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, and Yung-Chih Chen, 2016, January, "An Efficient Interpolation-based Projected Sum of Product Decomposition via Genetic Algorithm," Journal of Multiple-Valued Logic and Soft Computing, vol. 27, no. 1, pp. 1-19.
Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan, 2016, June, "Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays," IEEE Transactions on VLSI Systems (TVLSI), vol. 24, no. 6, pp. 2321-2334.
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suma Datta, and Vijaykrishnan Narayanan, 2016, September, "Area-aware Decomposition for Single-Electron Transistor Arrays," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 4, article 70.
Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, and Chiou-Ting Hsu, 2016, October, "Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks," IEEE Transactions on Multi-Scale Computing Systems, vol. 2 no. 4, pp. 225-233.
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan, 2015, December, "Synthesis for Width Minimization in the Single-Electron Transistor Array ," IEEE Transactions on VLSI Systems (TVLSI), vol. 32, no. 12, pp. 2862-2875.
Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen, 2015, April, "Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 4, pp. 615-628.
Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu, 2014, "Hybrid LUT and SOP reconfigurable architecture," Academia Sinica Journal of Information Science and Engineering (JISE), Vol. 30. I. 1, pp. 65-84.
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan, 2013, "A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no. 1, article 5.
Yung-Chih Chen, Chun-Yao Wang, and Ching-Yi Huang, 2013, "Verification of Reconfigurable Binary Decision Diagram-based Single-Electron Transistor Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 10, pp. 1473-1483.
Yung-Chih Chen, Chun-Yao Wang, 2012, February, "Logic Restructuring Using Node Addition and Removal," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 2, pp.260-270.
Yung-Chih Chen, Chun-Yao Wang, 2010, November, "Fast Node Merging with Don’t Cares Using Logic Implications,," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 11, pp. 1827-1832.
Yung-Chih Chen, Chun-Yao Wang, 2008, November, "An Implicit Approach to Minimizing Range-Equivalent Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 1942-1955.
Conference Papers
Ting-Yu Yeh, Yueh Cho, and Yung-Chih Chen, "An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification", IEEE Design Automation and Test in Europe, 2023.
RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, and TingTing Hwang, "Expanding In-Cone Obfuscated Tree for Anti SAT Attack", IEEE Design Automation and Test in Europe, 2023.
Yung-Chih Chen and Feng-Jie Chao, "Optimization of Reversible Logic Networks with Gate Sharing", Asia and South Pacific Design Automation Conference, 2023.
Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, and Jing-Yang Jou, "1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method," Asia and South Pacific Design Automation Conference, 2021. (Best Paper Nominee)
Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, and Shih-Chieh Chang, "Accuracy Tolerant Neural Networks Under Aggressive Power Optimization," IEEE Design Automation and Test in Europe, 2020.
Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng, "Don’t-Care-Based Node Minimization for Threshold Logic Networks," Design Automation Conference, 2020.
Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, and Chun-Yao Wang, "Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018. (Best Paper Award)
Fu-Lian Wong, Li-Cheng Zheng, and Yung-Chih Chen, "Optimization of Threshold Logic Networks with ODC-based Node Merging," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018.
Yung-Chih Chen, "Tree-Based Logic Encryption for Resisting SAT Attack," Asian Test Symposium, 2017.
Wen-Chun Zeng, Shih-Hsiang Liu, Yu-Da Chen, and Yung-Chih Chen, "A Counterexample-Based Debugging Method for Reconfigurable Single- Electron Transistor Arrays," IEEE International Conference on Electron Devices and Solid-State Circuits, 2017.
Yung-Chih Chen, Runyi Wang, and Yan-Ping Chang, "Fast Synthesis of Threshold Logic Networks with Optimization," Asia and South Pacific Design Automation Conference (ASPDAC), 2016, pp.486-491.
Yung-Chih Chen and Kung-Ming Ji, "SAT-based Complete Logic Implication with Application to Logic Optimization," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2014, pp. 1-4.
Yung-Chih Chen and Chun-Yao Wang, "Node Addition and Removal in the Presence of Don’t Cares", Design Automation Conference, pp. 505-510, June 2010. (Best Paper Nominee)