Advanced Logic Design Automation Lab @ NTUSTEE

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專題計畫名稱: 基於高斯消去法之邏輯電路逆向工程技術

T.-Y. Yeh, Y. Cho, and Y.-C. Chen, "An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification", DATE, 2023

Y.-C. Chen and F.-J. Chao, "Optimization of Reversible Logic Networks with Gate Sharing", ASP-DAC, 2023