Publication

*SCI, SCIE 구분은 통합 기준에 맞게 소급 적용함. (SCIE 로 통일하여 표기)

2021~2025

• Yunjae Oh, Inyoung Lee, Yunejae Suh, Daewoong Kang* and Il Hwan Cho*, "3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer," IEEE ACCESS. (SCIE, 2023)

• Daewoong Kang, Hyojin Park, Dae Hwan Kim, and Il Hwan Cho*,"Device characteristics of the select transistor in a vertical-NAND flash memory", Japanese Journal of Applied Physics. (SCIE, 2023)

• Hyojin Park, Inyoung Lee, Il Hwan Cho*, and Daewoong Kang*,"Improvement of Cell Characteristics using Controlling the Current Path in 3D NAND Flash", Japanese Journal of Applied Physics. (SCIE, 2023)

• Tae-Woong Jeong, Yun-Jae Oh, Seo-Yeon Chun, Dae Hwan Kim,Woojoo Lee*, and Il Hwan Cho*,"Investigation of p-type High Temperature Field Effect Transistor for CMOS Logic Application", Journal of Semiconductor Technology and Science. (SCIE, 2022)

• INYOUNG LEE, DAE HWAN KIM, DAEWOONG KANG* and IL HWAN CHO*, "Investigation of Poly Silicon Channel Variation in Vertical 3D NAND Flash Memory", IEEE ACCESS. (SCIE, 2022)

• Inyoung Lee 1 , Hyojin Park 1, Quan The Nguyen 1, Garam Kim 1 , Seongjae Cho 2,* and Ilhwan Cho 1*, "Optimization of Feedback FET with Asymmetric Source Drain Doping Profile", Micromachines. (SCIE, 2022)

• Ga Won Yang , Jingyu Park, Sungju Choi , Changwook Kim , Dong Myong Kim, Sung-Jin Choi , Jong-Ho Bae , Il Hwan Cho* , and Dae Hwan Kim*, "Total Subgap Range Density of States-Based Analysis of the Effect of Oxygen Flow Rate on the Bias Stress Instabilities in a-IGZO TFTs", IEEE TRANSACTIONS ON ELECTRON DEVICES. (SCIE, 2022)

• Quan The Nguyen, Deokjin Jang, Md. Hasan Raza Ansari , Garam Kim, Seongjae Cho , and Il Hwan Cho* ,"Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators", Japanese Journal of Applied Physics. (SCIE, 2021)

2016~2020

• Dong Chang Han, Deok Jin Jang, Jae Yoon Lee, Seongjae Cho*, and Il Hwan Cho*, "Investigation of modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics", Journal of Semiconductor Technology and Science. (SCIE, 2020)

• Daehyung Kim, Fahad Rashid, Yeonmo Cho, Manal S. Zaher, II Hwan Cho, Samir M. Hamdan, Cherlhyun Jeong* and Jong-Bong Lee*, "DNA skybridge: 3D structure producing a light sheet for high-throughput single-molecule imaging",Nucleic Acids Research. (SCIE, 2019)

• Jongmin Ha, Jae Yoon Lee, Myeongseon Kim, Seongjae Cho, and Il Hwan Cho*, "Investigation and Optimization of Double-gate MPI 1TDRAM with Gate-induced Drain Leakage Operation", Journal of Semiconductor Technology and Science. (SCIE, 2019)

• Myeongsun Kim, Jongmin Ha, Ikhyeon Kwon, Jae-Hee Han, Seongjae Cho,* and Il Hwan Cho*,"A Novel One-Transistor Dynamic Random-Access Memory (1T DRAM) Featuring Partially Inserted Wide-Bandgap Double Barriers for High-Temperature Applications", Micromachines. (SCIE, 2019)

• Ikhyeon Kwon, Hyuck-In Kwon, Il Hwan Cho*,"Development of high temperature operation silicon based MOSFET for harsh environment application", Results in Physics. (SCIE, 2018)

• Ikhyeon Kwon, M. Saif Islam, and Il Hwan Cho*,"Investigation of Non Volatile AlGaN/GaN Flash Memory for High Temperature Operation", Journal of Semiconductor Technology and Science. (SCIE, 2018)

• Jeong Hoon Jang, Xiangyu Wang, and Il Hwan Cho*,"An Alternative Simulation Program with Integrated Circuit Emphasis Model of Tunneling Field Effect Transistor Considering Ambipolar Characteristics", Journal of Nanoelectronics and Optoelectronics, (SCIE, 2018)

• XIANGYU WANG, Wonhee Cho, Hyoung Won Baac, Dongsun Seo, and Il Hwan Cho*,"Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall", Journal of Semiconductor Technology and Science. (SCIE, 2017)

• Asif Ali, Dongsun Seo, and Il Hwan Cho*,"Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate",Journal of Semiconductor Technology and Science. (SCIE, 2017)

• Daewoong Kang, Hyoungsoo Kim, Asif Ali, Youngchang Yoon and Il Hwan Cho*,"Analysis of the current path for a vertical NAND flash cell with program/erase states", Semiconductor Science and Technology. (SCIE, 2016)

2011~2015

• Songnam Lim, Jong-Ho Lee, Woo Young Choi, and Il Hwan Cho*, "Pull-In Voltage Modeling of Graphene Formed Nickel Nano Electro Mechanical Systems (NEMS)", Journal of Semiconductor Technology and Science. (SCIE, 2015)

• Il Hwan Cho, Hyogeun Shin, Hyunjoo Jenny Lee and Il-Joo Cho*, "Effects of Fabrication Process Variation on Impedance of Neural Probe Microelectrodes", Journal of Electrical Engineering & Technology. (SCIE, 2015)

• Ning Xi, Eou-Sik Cho, Woo Young Choi, and Il Hwan Cho*, "Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor", Japanese Journal of Applied Physics. (SCIE, 2014)

• Chun Woong Park, Chongdae Park, Woo Young Choi, Dongsun Seo, Cherlhyun Jeong,and Il Hwan Cho*,"Scaling Down Characteristics of Vertical Channel Phase Change Random Access Memory (VPCRAM)", Journal of Semiconductor Technology and Science. (SCIE, 2014)

• Hyun Gon Oh, Cherlhyun Jeong, and Il Hwan Cho*, "Thermal analysis of self-heati", ng in saddle MOSFET devices", Japanese Journal of Applied Physics. (SCIE, 2014)

• Ji Mi Eom, Hyun Gon Oh, Il Hwan Cho, Sang Jik Kwon, and Eou Sik Cho*," Effects of the Duty Ratio on the Niobium Oxide Film Deposited by Pulsed-DC Magnetron Sputtering Methods",  Journal of Nanoscience and Nanotechnology.  (SCIE, 2013)

• ChunWoong Park, Woo Young Choi, Jong-Ho Lee and Il Hwan Cho*, "Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall", Semiconductor Science and Technology. (SCIE, 2013)

• Byung Kyu Park,, Woo Young Choi, Eou Sik Cho, and Il Hwan Cho*, "Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application", Journal of Semiconductor Technology and Science. (SCIE, 2013)

• Woo Young Choi, Min Su Han, Bo ram Han, Dongsun Seo and Il Hwan Cho*, "Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory", IEICE Transactions on Electronics. (SCIE, 2013)

• Hyun Gon Oh, Kyung Soo Kim, JiMiEom, Sang Jik Kwon, EouSik Cho, Jong-Ho Lee, Il Hwan Cho*, "Low Frequency Noise Characteristics on Al/Nb2O5/p-type Schottky Diode Fabricated by Pulsed DC Magnetron Sputtering", Molecular Crystals and Liquid Crystals. (SCIE, 2013)

• Dae Hwan Kim, Sungwook Park, Yujeong Seo, Tae Geun Kim , Dong Myong Kim and Il Hwan Cho*, "Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory", Journal of Semiconductor Technology and Science. (SCIE, 2012)

• Kyung Soo Kim and Il Hwan Cho*, "Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array", Japanese Journal of Applied Physics. (SCIE, 2012)

• Jae-Min Lee, In-Tak Cho, Jong-Ho Lee, Soon-Gil Yoon, and Il Hwan Cho*, "Enhancement of Temperature Sensitivity for Metal–Insulator–Semiconductor Temperature Sensors by Using Bi2Mg2=3Nb4=3O7 Film", Japanese Journal of Applied Physics. (SCIE, 2012)

• Young Min Kim, Il Hwan Cho, Hyuck-In Kwon, and Jong-Ho Lee*, "Effects of Body Doping in a NAND Flash String without Source/Drain", Japanese Journal of Applied Physics. (SCIE, 2011)

• Yong Joo Jee and Il Hwan Cho*, "Modeling of Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory", Japanese Journal of Applied Physics. (SCIE, 2011)

• Jaeman Jang, Jae Chul Park, Dongsik Kong, Dong Myong Kim, Jang-Sik Lee, Byeong-Hyeok Sohn, Il Hwan Cho and Dae Hwan Kim* ,"Endurance Characteristics of Amorphous-InGaZnO Transparent Flash Memory With Gold Nanocrystal Storage Layer, IEEE TRANSACTIONS ON ELECTRON DEVICES. (SCIE, 2011)

• Kyung Soo Kim, Jongho Lee, and Il Hwan Cho*, "Highly Scalable Vertical Channel Phase Change Random Access Memory", Japanese Journal of Applied Physics. (SCIE, 2011)