KEYNOTE TALKS
KEYNOTE TALKS
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GENERAL INFORMATION
GENERAL INFORMATION
With the advancement in both computing architectures and process technology, many-core architectures can have thousands of cores into a single chip. This integration opens up a plethora of challenges, e.g., in terms of specialization and energy-focused implementations, and supports the spread of various applications and computational paradigms, ranging from multiprocessing to reconfigurable computing, from quantum computing to the emerging area of neuromorphic computing. Such a wild increase in the number of processing elements (PE) per chip, together with the growing architectural and workload heterogeneity, calls for efficient, versatile, scalable, and reliable communication infrastructures. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, the integration of a large number of PEs on a chip, or heterogeneous workloads. Novel techniques and architectures are needed to efficiently design and optimize the NoC and evaluate it at the network or system level.
The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of multi-core systems-on-chip. The workshop will focus on issues related to the design, analysis, testing, and application of on-chip networks.
Β REGISTRATION
Please, remember toΒ
register for the MICRO-56 SymposiumΒ
by Sep 28 to attend the Workshop.
IMPORTANT INFO
Abstract submission deadline
July 24, 2023
July 31, 2023
Full paper submission deadline
July 24, 2023
July 31, 2023
Author Notification
August 22, 2023
Camera Ready
September 1, 2023
NoCArc Workshop
October 28, 2023
CALL FOR PAPERS
SPECIAL ISSUE
The accepted conference papers will be invited for an extended journal version, to be published in a Journal TBD.
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