Abstract: The system-on-chip (SoC) is the pervasive architecture in the age of heterogeneous computing, but its energy-efficient performance comes at the cost of higher design complexity. The critical challenges of SoC design are in the integration and management of many heterogeneous components, including programmable cores and specialized hardware accelerators. The network-on-chip (NoC) plays a central role in addressing these challenges, both at design time and run time. We show how a simple but configurable NoC architecture is at the core of the design of ESP, an open-source research  platform for system-on-chip design. By implementing the protocol and shell paradigm of latency-insensitive design, the NoC supports the key properties of the ESP platform, namely: modularity, scalability, flexibility, and productivity. We illustrate our case with a series of examples from both our research and teaching activities.