The NGC-Lab is at the forefront of developing scaling technologies for chip design. Our innovative approach involves in-depth studies of 2.5D and 3D scaling technologies for next-generation computing. We are dedicated to overcoming the design challenges for high-speed processor design, low-latency edge computing, and high-bandwidth memory design. These are the lab's current ongoing projects.

• 3DIC Design and Modelling: 3DIC design addresses the declining transistor density for advanced process nodes. Modeling of 3DIC creates opportunities to study the stress, thermal, and signal integrity-related issues arising during the IC design and allows the study of mitigation techniques to address them.

• Hardware Accelerators: To deploy AI models, we need robust edge computing nodes powered by hardware accelerators. Designing existing hardware accelerators with 3DIC techniques can address potential near- and in-memory computing issues. These Hardware accelerators provide low-latency and cost-effective inference generation for AI applications such as Agriculture, Autonomous Driving, and Biomedical Applications.