Hands-on Session

Hands-on Session: 11:30 - 17:30

Making use of SpiNNaker hardware for neural network simulations and neuromorphic applications 

The SpiNNaker neuromorphic architecture allows the efficient execution of a diverse range of neural network models and algorithms. Aiming to facilitate the implementation of new neuron models and synaptic plasticity rules on SpiNNaker, we introduce NESTML: a domain-specific modeling language that is combined with a powerful code generation toolchain. Once a model is formulated in the generic NESTML syntax, it can be simulated on a range of supported platforms, including GPUs, HPC systems, and SpiNNaker. In an interactive Jupyter Notebook-based tutorial, we will use the SpiNNaker platform provided via the EBRAINS cloud infrastructure to formulate and simulate custom NESTML models.

Following that, we will have an outlook on the capabilities of the second generation of the SpiNNaker hardware, access to which will soon be available at the Jülich Supercomputing Centre. To this end, in a live demo, the setup and simulation of neural network models as well as the use of spiking neural networks to algorithmically solve optimization problems will be showcased on SpiNNaker2. The workshop will conclude with a summary of the key aspects for using both the first and second generation SpiNNaker systems.

Embedded AI for IoT applications with the C1 Pulsar Neuromorphic Micro-controller 

Neuromorphic processors promise always-on intelligence right at the sensor, but turning trained network into an efficient embedded application on real silicon is still a nuanced challenge for many engineers. This hands-on session will offer participants a practical experience from model to embedded hardware using Innatera's technology.

The session opens with an introduction to Innatera's neuromorphic technology and its C1 Pulsar micro-controller, which brings together Spiking Neural Network acceleration, CNN acceleration and a RISC-V core together in one chip to deliver sensing and inference at microwatt power levels. Speakers will discuss current practice in mapping different kinds of embedded AI solutions onto Innatera hardware and share experiences from deploying them in ultra-low-power IoT applications.

Participants will have the opportunity to work with Talamo, Innatera's software development kit for embedded AI applications. Talamo builds on PyTorch, so anyone familiar with conventional deep learning can build a complete pipeline from preprocessing and spike encoding to the spiking network and decoder. They can then train, quantize, and compile it for the chip without prior experience with spiking networks. A hardware simulator will let everyone run and inspect their models directly on a laptop. 

The final part of the session will focus on some measurement profiling work. Innatera will provide cloud access to Pulsar hardware, so participants can deploy their own networks on a physical chip and instrument measurements on silicon. Participants will see how to measure e2e latency and power consumption, how to make sense out of these numbers, and how their algorithm/model design choices affect these measurements.  

By the end of the session, attendees will have taken a model from training all the way to execution on a neuromorphic chip, and will leave with practical guidelines for building efficient applications on Innatera hardware.

Building Blocks for Neuromorphic Chips: Generating Compute-in-Memory Macros and Integrating Them into an SoC

Neuromorphic and compute-in-memory (CiM) architectures rely on placing memory close to computation, and every new design needs memory blocks sized and connected for its purpose. Creating these blocks by hand is slow and error-prone, which makes design automation increasingly important for neuromorphic hardware. In this hands-on session, Ximplic Systems offers a practical look at one part of that process: automatically generating a CiM macro and integrating it into a system-on-chip (SoC). 

Participants choose a CiM configuration, such as [number of words and word width], and use Ximplic's memory generator to produce the corresponding macro. They then connect the macro to a provided SoC and run a simple test to verify that it performs its computation correctly within the system. The steps are guided and deliberately simple, so participants can focus on how CiM macro generation and SoC integration fit together, and what this means for building larger neuromorphic architectures.