Ultra-low-complexity Technologies for Advanced Driving Assistance System (ADAS) 

Design and Implementation of a Hybrid Hardware Accelerator Architecture for Convolutional Neural Network and Large Language Model 

Pipeline Optimization Design and Implementation of Hardware Architecture for Multi-Head Self-Attention Mechanism in Large Language Model Acceleration

Optimized Hardware Architecture and Implementation for Softmax Accelerator for LLMs 

Implementation of Cross-Layer Convolution Pipeline Extensible and Modularized Processing Unit Hardware Architecture for AI Accelerator 

Optimized Hardware Design and Implementation for Binary Neural Network 

Winograd Hardware Architecture and Implementation for Binarized Neural Network 

Dynamic Processing Element Optimization in Tile-grained Pipelined Convolutional Neural Network Accelerator 

Layer Fusion Optimization and Hardware Architecture Implementation for AI Accelerator 

A Lossless Winograd Hardware Architecture and Implementation for Convolutional Neural Network Accelerator 

High Efficiency Accelerator Hardware Architecture Implementation for Lightened Convolutional Neural Network

Tile-grained Pipelined Hardware Architecture and Implementation for Convolutional Neural Network Accelerator 

A Flexible and Efficient Hardware Architecture and Implementation for Multiple CNNs Accelerator 

Extensible and Modularized Hardware Architecture Design and Chip Implementation for AI Accelerator

Convolution Neutral Network Lightening and Hardware Architecture Acceleration Design

High Energy Efficiency Hardware Acceleration Architecture Design for Sparse CNN

System Integration and Optimization of AI Hardware Acceleration Architecture for Object Detection

Extensible and Modularized Processing Unit Hardware Architecture Design and Implementation for AI Accelerator

Hardware Implementation on FPGA Development Platform for Dental Pathological Recognition System

Using Image Augmentation to Improve the Accuracy of Residual Roots in Dental Pathological Recognition System

Hetero Layer Fusion Based Architecture Design and Implementation for Deep Learning Accelerator

Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN

Deep Learning Accelerator Architecture Integration and Implementation

High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator

Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator

Cordic Based Hardware Implementation for Object Region Layer of Tiny Yolo V2

Low Complexity Hough Transform Line Segmentation for Parking Grid Detection

High Throughput Hardware Implementation for Deep Learning AI Accelerator

High Efficient Hardware Implementation of Selective Search for AI Accelerator

Low-Complexity People Counting for Surveillance System

High Efficiency Sensing Technology for Road Surface Detection in Nighttime

Fast Vehicle Plate Detection & Recognitionfor Parking Management System

A Fast Hough Transform Using Additive Region Segmentation

Feature-based Pattern Matching for Pedestrian Detection and Recognition

Hardware Implementation of Low Complexity Feature Based License Plate Recognition System

Ultra Low Complexity Algorithm for Lane Departure Warning System

Hardware Implementation of Programmable Fast Algorithm for Object Detection

Hardware Implementation for Programmable Object Detection and Classification

A Hardware Sharing Architecture of Deblocking Filter for VP8, H.264/AVC and HEVC Video Coding

A Hardware Implementation of Object-based Stereo Matching Using Adjustable-crossfor Depth Estimation

Image Processing Based Algorithm for Traffic Lights Control System

A Hardware Architecture of Adaptive ROI for Intelligent Vehicles

A Hardware Architecture of Feature Extraction for Intelligent Vehicles

A Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Coding

An Efficient Background Extraction and Object Segmentation Algorithm for Realtime Applications

Hardware Implementation of Adaptive Stitching System for 360 Degree Dynamic Panoramic Video

Adaptive Wide Angle Image Distortion Correction and Panoramic Stitching System

FPGA Hardware Implementation for Vehicle License Plate Recognition System

Hardware Implementation on FPGA Development Platform for AI Crowd Control Detection System

Image Augmentation Based on CycleGAN to Improve The Accuracy of Caries in Dental Pathological Recognition System

Hardware and Software System Integration and Implementation on FPGA Platform for Deep Learning Accelerator