Speaker Information
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Professor, Department of Electrical and Computer Engineering, Utah State University
Research Interests:
VLSI Design Automation Circuit-Architectural Co-design
Presentation Title:
STRIVE: Fault Detection and Correction in a Low-Power Tensor Processing Unit
Abstract:
Rapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For improved energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However, low power AI accelerators suffer from diminishing reliability as we push the operating boundaries of deploying these systems. Operating at LPC causes increased delay sensitivity to Process Variation (PV) causing frequent faults in the DNN. In this talk, we will demonstrate the vulnerability of DNNs to delay faults, substantially lowering the prediction accuracy. To overcome delay faults, we present STRIVE—a post-fabrication fault detection and reactive error reduction technique for deep neural networks. We also introduce a time-borrow correction technique to ensure error-free DNN computations.
Brief Biography of Speaker
Dr. Sanghamitra Roy is a Professor in the ECE department at Utah State University. She received her Ph.D. degree in Electrical Engineering from the University of Wisconsin-Madison. She received her M.S. degree in Computer Engineering from Northwestern University. Dr. Roy has authored over 90 peer reviewed publications in top tier journals and conferences in computer systems design. She serves in the editorial boards of the IEEE Design and Test Magazine and the Journal of Low Power Electronics and Applications. She has won Best Paper Award nominations at DATE-2011, ICCAD-2005, VLSI Design-2010, ESWEEK CODES-2014 and DATE-2018. She has won the Best Paper Award at ICCD-2012. She received the NSF CAREER Award in 2013. Dr. Roy was named in the “125 People of Impact” --- the list of most influential alumni to graduate from the University of Wisconsin-Madison. She is an inventor in 12 issued US patents. Dr. Roy’s research is funded primarily by the National Science Foundation, and also by Micron, USTAR, among others.
Professor, Department of Electrical and Computer Engineering, Utah State University
Research Interests:
VLSI Design and Automation, Circuit-Architectural Co-design
Presentation Title:
Power Efficient AI Hardware Design: A Circuit-Architectural Pathway
Abstract:
In the modern world driven by pervasive Artificial Intelligence (AI) applications, the demand for energy efficiency is always on the rise. For example, inefficiencies in the conventional architectures led to the rapid proliferation of domain-specific architectures such as Tensor Processor Unit (TPU) geared towards AI applications. On the other hand,
Near-Threshold Computing (NTC) has been a prominent low power design paradigm at the device level, offering a substantial reduction in power consumption through aggressive underscaling of the chip supply voltage, in comparison to the conventional Super-Threshold Computing (STC). However, the extreme sensitivity to manufacturing process variation (PV) and inherent slow down of the speed in the transistor operated in this regime, results in serious reliability and performance problems at the circuit-architecture level.
In this talk, I will outline a novel approach, termed as GreenTPU, combining these two technology trends to ensure a high inference accuracy at a low-voltage operation. GreenTPU dynamically identifies error-causing patterns in input data that are streamed into a TPU compute engine. Subsequently, it prevents further timing errors from the same sequence by pro-actively boosting the operating voltage of the specific multiplier-and-accumulator units in the TPU. Compared to a cutting-edge timing error mitigation technique for TPUs, GreenTPU enables 2X-3X higher performance in an NTC TPU, with a minimal loss in the inference accuracy.
Brief Biography of Speaker
Koushik Chakraborty received the B.Tech. degree from IIT Kanpur, India in 2000, and the M.S. and Ph.D. degrees from the University of Wisconsin–Madison, Madison, WI, USA, in 2004 and 2008, respectively. He is a Professor in the Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA. His current research interests are cross-layer circuit-architectural techniques to improve the energy efficiency and reliability of domain specific architectures. His research is funded by National Science Foundation and Micron Incorporation. He has published over 90 peer-reviewed conference and journal papers. Dr. Chakraborty received the Best Paper Award/Nomination at the 2010 VLSID, the 2011 DATE, 2012 ICCD, 2014 CODES-ISSS, and 2018 DATE Conference. He regularly serves in Technical Program Committee of DAC, DATE, ICCAD, and other top conferences. Recently, he was the track chair for DAC 2023.