Rapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For improved energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However, low power AI accelerators suffer from diminishing reliability as we push the operating boundaries of deploying these systems. Operating at LPC causes increased delay sensitivity to Process Variation (PV) causing frequent faults in the DNN. In this talk, we will demonstrate the vulnerability of DNNs to delay faults, substantially lowering the prediction accuracy. To overcome delay faults, we present STRIVE—a post-fabrication fault detection and reactive error reduction technique for deep neural networks. We also introduce a time-borrow correction technique to ensure  error-free DNN computations.

Brief Biography of Speaker 

In the modern world driven by pervasive Artificial Intelligence (AI) applications, the demand for energy efficiency is always on the rise. For example, inefficiencies in the conventional architectures led to the rapid proliferation of domain-specific architectures such as Tensor Processor Unit (TPU) geared towards AI applications. On the other hand,

Near-Threshold Computing (NTC) has been a prominent low power design paradigm at the device level, offering a substantial reduction in power consumption through aggressive underscaling of the chip supply voltage, in comparison to the conventional Super-Threshold Computing (STC). However, the extreme sensitivity to manufacturing process variation (PV) and inherent slow down of the speed in the transistor operated in this regime, results in serious reliability and performance problems at the circuit-architecture level.

In this talk, I will outline a novel approach, termed as GreenTPU, combining these two technology trends to ensure a high inference accuracy at a low-voltage operation. GreenTPU dynamically identifies error-causing patterns in input data that are streamed into a TPU compute engine. Subsequently, it prevents further timing errors from the same sequence by pro-actively boosting the operating voltage of the specific multiplier-and-accumulator units in the TPU. Compared to a cutting-edge timing error mitigation technique for TPUs, GreenTPU enables 2X-3X higher performance in an NTC TPU, with a minimal loss in the inference accuracy.

Brief Biography of Speaker