International Journals
11. (Sole author, SCIE, IF: 3.476) N.-S. Kim, “A 10-Bit, 600 MS/s Multi-Mode Direct-Sampling DAC-Based Transmitter,” IEEE Access, vol. 10, pp. 125696–125706, 2022.
10. (Corresponding author, SCIE, IF: 2.312) J. Choi and N.-S. Kim, “A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, issue. 12, pp. 2098–2109, 2021.
9. (Sole author, SCI, IF: 3.413) N.-S. Kim, “A Digital-Intensive Extended-Range Dual-Mode BLE5.0 and IEEE802.15.4 Transceiver SoC,” IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 68, issue. 6, pp. 2020–2029, 2020.
8. (First author, SCI, IF: 3.756) N.-S. Kim and J. M. Rabaey, “A 3.1-10.6 GHz, 57-Bands CMOS Frequency Synthesizer for UWB-based Cognitive,” IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 66, issue. 9, pp. 4134–4146, 2018.
7. (First author, SCI, IF: 3.934) N.-S. Kim and J. M. Rabaey, “A Dual-Resolution Wavelet-based Energy Detection Spectrum Sensing for UWB-based Cognitive Radios,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 65, issue. 7, pp. 2279–2292, 2018.
6. (Co-author, SCI, IF: 4.075) C.-W. Yao, R. Ni, C. Lau, W. Wu, K. Godbole, Y. Zuo, S. Ko, N.-S. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. W. Son and T. B. Cho, “A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 12, pp. 3446–3457, 2017.
5. (First author, SCI, IF: 4.181) N.-S. Kim and J. M. Rabaey, “A High Data-Rate Energy Efficient Triple-Channel UWB-Based Cognitive Radio,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 809–820, 2016.
4. (First author, SSCI, IF: 2.070) N.-S. Kim, K. Chung, S. Ahn, J. W. Yu, and K. Choi, “Denoising Traffic Collision Data Using Ensemble Empirical Mode Decomposition and Its Application for Constructing Continuous Risk Profile,” Accident Analysis & Prevention (AAP), vol. 71, pp. 29–37, 2014.
3. (Co-author, SCI, IF: 1.756) Y. Yoon, H. Kwon, J. Lee, B. Park, N.-S. Kim, U. Cho, and H. Byun, “Synchronous mirror delay for multiphase locking,” IEEE Journal of Solid-State Circuits (JSSC), vol. 39, no. 1, pp. 150–156, 2004.
2. (Co-author, SCI, IF: 2.035) U. Cho, T. Kim, Y. Yoon, J. Lee, D. Bae, N.-S. Kim, K. Kim, Y. Son, J. Yang, K. Sohn, S. Kim, I. Lee, K. Lee, T. Kang, S. Kim, K. Ahn, and H. Byun, “A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM,” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 11, pp. 1943–1951, 2003.
1. (Co-author, SCI, IF: 0.418) J. Lee, N.-S. Kim, I. Kim, and B. Park, “Fabrication of Silicon Field Emitter Arrays Combined with HVTFT at Low,” Journal of the Korean Physical Society (JKPS), vol. 35, pp. 1102–1105, 1999.
International Conference Proceedings
20. N.-S. Kim, M.-G. Kim, A. Verma, G. Seol, S. Kim, S. Lee, C. Lo, J. Lee, J. Han, I. Jo, C. Kim, C.-W. Yao, and J. Lee, “A 1.04 - 4V, Digital-Intensive Dual-mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2019, pp. 271-274.
19. J. Choi, N.-S. Kim, J.Han, and T. B. Cho, "A 0.46-2.1GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23dBm Integrated PAs in 28nm CMOS,” in IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2018, pp. 299-302.
18. C.-W. Yao, W. F. Loke, Ronghua Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N.-S. Kim, S. Han, I.Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. W. Son, T. B. Cho, “A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2017, pp. 422–423.
17. N.-S. Kim and Jan M. Rabaey, “A 3.1 - 10.6GHz wavelet-based dual resolution spectrum sensing with harmonic rejection mixers,” in European Solid-State Circuits Conference (ESSCIRC), Sept 2015, pp. 303–306.
16. N.-S. Kim and Jan M. Rabaey, “A 1Gb/s Energy Efficient Triple-Channel UWB-based Cognitive Radio,” in IEEE Symp. VLSI Circuits Dig. of Tech. Papers, Jun. 2015, pp. 96-97.
15. N.-S. Kim and Jan M. Rabaey, “A 3-10 mW, 3.1-10.6 GHz Integer-N QPLL with Reference Spur Reduction Technique for UWB-based Cognitive Radios,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2015, pp. 67–70.
14. N.-S. Kim, K. Chung, S. Ahn, J. W. Yu, and K. Choi, “Denoising traffic collision data using Ensemble Empirical Mode Decomposition (EEMD) and its application for constructing Continuous Risk Profile (CRP),” in Transportation Research Board (TRB) 93rd Annual Meeting, no. 14-2119. 2014.
13. N.-S. Kim and Jan M. Rabaey, "A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator," in IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2013, pp. 329-332.
12. S.Y.Chen, N.-S. Kim, and J.Rabaey, “A 10b 600MS/s multi-mode CMOS DAC for multiple Nyquist zone operation,” in IEEE Symp. VLSI Circuits Dig. of Tech. Papers, Jun. 2011, pp. 66-67.
11. S.Y.Chen, N.-S. Kim, and J.Rabaey, “Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis,” in IEEE Workshop on Signal Processing Systems (SiPS). Oct. 2008, pp. 112-117.
10. H.Yang, K.Park, N.-S. Kim, J.Kim, J.Kim, B.Kong, J.Choi, and Y.Jun, “A Phase-Locked Loop with Reference Clock Based Locking Time for Above 2.0Gb/s/pin DRAM Interface,” in International SoC Design Conference (ISOCC), Oct. 2007, pp.103-106.
9. H.Yu, N.-S. Kim, Y.Son, Y.Kim, H.Kim, U.Cho, and H.Byun, “A SRAM Core Architecture with Adaptive Cell Bias Scheme,” in IEEE Symp. VLSI Circuits Dig. of Tech. Papers, Jun. 2006, pp. 128-129.
8. H.Kim, N.-S. Kim, H.Yu, U.Cho, and H.Byun, “SMD-based internal clock generator for memory test,” in International SoC Design Conference (ISOCC), Oct. 2005, pp.293-296.
7. N.-S. Kim, U.Cho, and H.Byun, “Low Voltage Wide Range DLL-based Quad-Phase Core Clock Generator for High Speed Network SRAM Application,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2005, pp. 533–536.
6. N.-S. Kim, U.Cho, and H.Byun, “A pseudo differential CMOS receiver insensitive to input common mode level,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 440-443.
5. N.-S. Kim, Y.Yoon, U.Cho, and H.Byun, “Programmable and automatically adjustable on die terminator for DDR3 SRAM interface,” ” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2003, pp. 391–394.
4. N.-S. Kim, U.Cho, and H.Byun, “New dynamic logic level converters for high performance application,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2003, pp. 93-96.
3. U.Cho, T.Kim, Y.Yoon, J.Lee, D.Bae, N.-S. Kim, K.Kim, Y.Son, J.Yang, K.Shon, S.Kim, I.Lee, K.Lee, T.Kang, S.Kim, K.Ahn, and H.Byun, “A 1.2V 1.5Gbp/s 72Mb DDR3 SRAM,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2003, pp. 300–301.
2. S.Kim, N.-S. Kim, T.Kim, U.Cho, H.Byun, and S.Kim, “Programmable Digital On-Chip Terminator,” in International Technical Conference on Circuits Systems, Computers and Communications (ITC-CSCC), Jul. 2002, pp. 1572-1575.
1. Y.Yoon, J.Lee, B.Park, N.-S. Kim, U.Cho, and H.Byun, “Synchronous Mirror Delay for Multi-phase Locking”, in Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Jun. 2002, pp. 33-36.
US Patents
35. S.-W. Lee and N.-S. Kim, “Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation,” Aug. 2021, US11086345B2.
34. S.-W. Lee and N.-S. Kim, “Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation,” Aug. 2020, US10747250B2.
33. J.-W. Choi and N.-S. Kim, “Wide-range local oscillator (LO) generators and apparatuses including the same,” Jan. 2020, US10547315B2.
32. N.-S. Kim, S.-S. Ko, and B.-J. Kang, “Wide-range local oscillator (LO) generators and apparatuses including the same,” Jun. 2019, US10326460B2.
31. N.-S. Kim, “Digital-to-time converter and operating method thereof,” Nov. 2018, US10122378B2.
30. N.-S. Kim and U.Cho, “Delay-locked loop circuits and method for generating transmission core clock signals,” Oct. 2010, US7825710B2.
29. N.-S. Kim, H.Yu, and U.Cho, “Data line layout and line driving method in semiconductor memory device,” Apr. 2010, US7697314B2.
28. N.-S. Kim, J.Lee, H.Yu, and U.Cho, “Semiconductor memory device with hierarchical bit line structure,” Feb. 2010, US7656723B2.
27. N.-S. Kim, J.Lee, H.Yu, and U.Cho, “Semiconductor memory device with hierarchical bit line structure,” Nov. 2009, US7616512B2.
26. N.-S. Kim and U.Cho, “Phase interpolation circuit and method of generating phase interpolation signal,” Jun. 2009, US7551013B2.
25. N.-S. Kim, J.Lee, H.Yu, and U.Cho, “Semiconductor memory device with hierarchical bit line structure,” Feb. 2009, US7489570B2.
24. N.-S. Kim, Y.Yoon, and U.Cho, “Amplifier circuit having constant output swing range and stable delay time,” Jul. 2008, US7400177B2.
23. M.Choi, N.-S. Kim, and C.Park, “Programmable impedance controller and method for operating,” Oct. 2007, US7288966B2.
22. N.-S. Kim, Y.Yoon, and U.Cho, “Amplifier circuit having constant output swing range and stable delay time,” Mar. 2007, US7187214B2.
21. T.Kim, N.-S. Kim, and U.Cho, “Semiconductor device with impedance control circuit,” Jan. 2007, US7170318B2.
20. N.-S. Kim, Y.Yoon, and U.Cho, “Apparatus for generating internal clock signal,” Dec. 2006, US7154312B2.
19. N.-S. Kim, U.Cho, and Y.Yoon, “Semiconductor memory device capable of generating variable clock signals according to modes of operation,” Mar. 2006, US7016257B2.
18. N.-S. Kim, Y.Yoon, and U.Cho, “Synchronous mirror delay circuit and semiconductor integrated circuit device having the same,” Jan. 2006, US6992514B2.
17. T.Kim, U.Cho, and N.-S. Kim, “Semiconductor device with impedance control circuit,” Sep. 2005, US6947336B2.
16. T.Kim, Y.Yoon, N.-S. Kim, and K.Lee, “Synchronous mirror delay circuit with adjustable locking range,” Aug. 2005, US6933758B2.
15. N.-S. Kim, T.Kim, and U.Cho, “Integrated circuit with on-chip termination,” Aug. 2005, US6930508B2.
14. N.-S. Kim, and K.Lee, “Method of outputting internal information through test pin of semiconductor memory and output circuit thereof,” Dec. 2004, US6834366B2
13. N.-S. Kim, and J.Lee, “Programmable reference voltage generating circuit,” Oct. 2004, US6806763B2.
12. N.-S. Kim, and Y.Yoon, “Digitally controllable internal clock generating circuit of semiconductor memory device and method for same,” Dec. 2003, US6661272B2.
11. N.-S. Kim, and U.Cho, “Programmable impedance control circuit,” Dec. 2003, US6661250B2.
10. N.-S. Kim, and U.Cho, “Programmable termination circuit and method,” Nov. 2003, US6642740B2.
9. J.Park, U.Cho, and N.-S. Kim, “Internal clock generating circuit of semiconductor memory device and method thereof,” Sep. 2003, US6628155B2.
8. Y.Yoon, U.Cho, J.Park, and N.-S. Kim, “Circuits and methods for generating internal clock signal of intermediate phase relative to external clock,” Sep. 2003, US6617894B2.
7. N.-S. Kim, U.Cho, and K.Lee, “Signal converting system having level converter for use in high speed semiconductor device and method therefore,” Jun. 2003, US6583647B2.
6. N.-S. Kim, and J.Park, “Method for generating internal clock of semiconductor memory device and circuit thereof,” Jun. 2003, US6577175B2.
5. N.-S. Kim, and U.Cho, “Impedance control circuit,” Jun. 2003, US6573746B2.
4. N.-S. Kim, and U.Cho, “Impedance updating apparatus of termination circuit and impedance updating method thereof,” Apr. 2003, US6556038B2.
3. N.-S. Kim, and U.Cho, “Programmable impedance control circuit,” Feb. 2003, US6525558B2.
2. J.Park, and N.-S. Kim, “Delay circuit using current source,” Jan. 2003, US6509774B2.
1. N.-S. Kim, and U.Cho, “Programmable impedance control circuit and method thereof,” Aug. 2002, US6429679B1.