Publication Lists
PhD. EE NCTU
Thesis: Multi-Phase Timing Skew Calibration and Its Application to Time-Interleaved ADCs
MS. EE NCTU
Thesis: A 5GHz CMOS Frequency Synthesizer Design for IEEE 802.11a
Quantity of 1st Author: 3
[1] C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-Bit 16-GS/s time interleaved ADC using digital background calibration techniques,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 848-858, Apr. 2011.
[2] C.-C. Huang, C.-Y.Wang, and J.-T.Wu, “A CMOS6-bit 16-GS/s time interleaved ADC with digital background calibration,” in Symp. VLSI Circuits Dig. Tech. Papers, 2010, pp. 159–160.
[3] C.-Y. Wang and J.-T. Wu, “A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection,” IEEE Transactions on Circuits and Systems – I: Regular Papers, Vol. 56, No. 6, pp. 1102-1114, June 2009.
[4] J.-L. Fan, C.-Y. Wang, and J-T Wu, “A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs,” IEEE Trans. Circuits Syst. I, vol. 54, no. 6, pp. 1213-1223, June 2007.
[5] C.-Y. Wang and J.-T. Wu, “A background timing-skew calibration technique for time-interleaved analog-to-digital converters,” IEEE Trans. Circuits Syst. II, Reg. Papers, vol. 53, no. 4, pp. 299–303, Apr. 2006.
[6] C.-Y. Wang, P.-H. Hsieh, and Z.-C. Wang, “Analog Convolution Circuit System Implemented With Capacitor Array Superposition,” IEEE Open J. Circuits Syst., vol. 7, pp. 60–68, Feb. 2026.