- # denotes the corresponding author, and * denotes that these authors contributed equally to this work.
- [J*], [C*], and [*U*] denote journal publications, conference proceedings, and works under preparation.
Embedded Files
Under Preparation
[JU1] Y. Song, K. Ha, H.-G. Ko, D.-K. Jeong, and M.-S. Choo#
IEEE Journal of Solid-State Circuits (JSSC)
2024
[J17] and M.-S. Choo and # (submitted, TCAS-II)
[J16] and M.-S. Choo# (submitted, TCAS-II)
[J15] and M.-S. Choo# (submitted, TCAS-II)
[J14] and M.-S. Choo# (accepted, TCAS-I)
[J13] and M.-S. Choo# (accepted, TCAS-II)
[J12] and M.-S. Choo# (accepted, JSTS)
[C13] and M.-S. Choo# (ISOCC)
[C12] and M.-S. Choo# (DAC)
[C11] and M.-S. Choo# (ICEIC)
[C10] and M.-S. Choo# (ICEIC)
[C9] and M.-S. Choo# (ICEIC)
2023
[C8] S.-U. Kang, J.-W. Han, and M.-S. Choo#
"Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application"
International Conference on Electronics, Information, and Communications (ICEIC) [Link]
[C7] I.-W. Jang and M.-S. Choo#
"Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Inside Digital Filter"
International Conference on Electronics, Information, and Communications (ICEIC) [Link]
2022
[J11] D. Lee, K. Park, J. Han#, and M.-S. Choo#
"An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies"
IEEE Access [Link]
2021
[J10] M.-S. Choo, S. Kim, H.-G. Ko, S.-Y. Cho, K. Park, J. Lee, S. Shin, H. Chi, and D.-K. Jeong#
"A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier with Real-Time Offset Tracking using Time-Division Dual Calibration"
IEEE Journal of Solid-State Circuits (JSSC) [Link]
[J9] K. Park, K. Lee, S.-Y. Cho, J. Lee, J. Hwang, M.-S. Choo, and D.-K. Jeong#
"A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS"
IEEE Journal of Solid-State Circuits (JSSC) [Link]
2020
[J8] M.-S. Choo and D.-K. Jeong#
"Review of Injection-Locked Oscillators"
Journal of Semiconductor Engineering (JSE), Inaugural issue [Link]
2019
[J7] M.-S. Choo, Y. Song, S.-Y. Cho, H.-G. Ko, K. Park, and D.-K. Jeong#
"A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response"
IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II) [Link]
[J6] M.-S. Choo, K. Park, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong#
"A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology"
IEEE Journal of Solid-State Circuits (JSSC) [Link]
[J5] M. Choi, C.-H. Kye, J. Oh, M.-S. Choo, and D.-K. Jeong#
"A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator"
IEEE Solid-State Circuits Letters (SSC-L) [Link]
[C6] K. Park, K. Lee, S.-Y. Cho, J. Lee, J. Hwang, M.-S. Choo, and D.-K. Jeong
"A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS"
IEEE Symposium on VLSI Circuits (VLSIC) [Link]
[C5] M. Choi, C.-H. Kye, J. Oh, M.-S. Choo, and D.-K. Jeong
"A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time"
IEEE International Solid-State Circuits Conference (ISSCC) [Link]
2018
[C4] M.-S. Choo, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong
"A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop"
IEEE Asian Solid-State Circuits Conference (A-SSCC), invited to JSSC [Link]
[J4] M.-S. Choo, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong#
"An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter"
IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II) [Link]
[J3] S.-Y. Cho, S. Kim, M.-S. Choo, H.-G. Ko, J. Lee, W. Bae, and D.-K. Jeong#
"A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection"
IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I) [Link]
2017
[J2] K. Park, J. Lee, K. Lee, M.-S. Choo, S. Jang, S.-H. Chu, S. Kim, and D.-K. Jeong#
"A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel"
IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II) [Link]
[C3] S. Kim, H.-G. Ko, S.-Y. Cho, J. Lee, S. Shin, M.-S. Choo, H. Chi, and D.-K. Jeong
"A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration"
IEEE International Solid-State Circuits Conference (ISSCC) [Link]
2016
[J1] S. Kim, S. Jang, S.-Y. Cho, M.-S. Choo, G.-S. Jeong, W. Bae, and D.-K. Jeong#
"A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique"
Journal of Semiconductor Technology and Science (JSTS) [Link]
[C2] J. Lee, S. Kim, M.-S. Choo, S.-Y. Cho, H.-G. Ko, D.-K. Jeong
"A theoretical analysis of phase shift in pulse injection-locked oscillators"
IEEE International Symposium on Circuits and Systems (ISCAS) [Link]
2015
[C1] S.-Y. Cho, S. Kim, M.-S. Choo, J. Lee, H.-G. Ko, S. Jang, S.-H. Chu, W. Bae, Y. Kim, and D.-K. Jeong
"A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection"
European Solid-State Circuits Conference (ESSCIRC) [Link]
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