Post-CMOS logic designs, in-memory computing, FPGA, asynchronous digital logic, and machine learning (ML) hardware.
[CP: GLSVLSI'25] M. Hossain and A. Tatulian, "PeerCollate: A Peer-Centered Team Learning Approach to Digitized STEM Lab Activities and Assessments," ACM Great Lakes Symposium on VLSI, New Orleans, LA, USA, 2025 (Accepted).
[D: Ph. D.'24] M. Hossain, "Adaptive Beyond Von-Neumann Computing Devices and Reconfigurable Architectures for Edge Computing Applications," University of Central Florida, 2024. [Dissertation]
[J: Front. Elec.'24] M. A. Chowdhury, M. Hossain, C. Mastrangelo, R. F. DeMara, and S. Salehi, "S-Tune: SOT-MTJ manufacturing parameters tuning for securing the next generation of computing," Frontiers in Electronics, Vol. 5, 2024, doi: 10.3389/felec.2024.1409548. [Paper]
[CP: GLSVLSI'24] R. Yarnell, M. Hossain, et al., "Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level Synthesis," ACM Great Lakes Symposium on VLSI, NY, USA, 2024, pp. 343-346, doi: 10.1145/3649476.3658786. [Paper]
[CP: ISQED'24] M. Hossain, M. A. Chowdhury, R. F. DeMara, and S. Salehi, "Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective," 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, pp. 1-5, doi: 10.1109/ISQED60706.2024.10528782. [Paper]
[CP: ISCAS'23] M. Hossain, A. Tatulian, H. R. Thummala, R. F. DeMara, and S. Salehi, "Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy," 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181529. [Paper]
[CP: ISQED'23] R. Yarnell, M. Hossain, and R. F. DeMara, "Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator Framework," 2023 24th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2023, pp. 1-7, doi: 10.1109/ISQED57927.2023.10129324. [Paper]
[J: TETC'23] M. Hossain, A. Tatulian, S. Sheikhfaal, H. R. Thummala, and R. F. DeMara, "Scalable Reasoning and Sensing Using Processing-In-Memory With Hybrid Spin/CMOS-Based Analog/Digital Blocks," in IEEE Transactions on Emerging Topics in Computing, vol. 11, no. 2, pp. 343-357, 1 April-June 2023, doi: 10.1109/TETC.2022.3212341. [Paper]
[CP: SouthEast Con.'22] D. Crumley, M. Hossain, K. Martin, F. Ivey, R. Yarnell, R. F. DeMara, and Y. Bai , "Rehosting YOLOv2 Framework for Reconfigurable Fabric-based Acceleration," SoutheastCon 2022, Mobile, AL, USA, 2022, pp. 445-446, doi: 10.1109/SoutheastCon48659.2022.9763979. [Paper]
[J: TED'22] M. Liu, P. Borulkar, M. Hossain, R. F. Demara, and Y. Bai, "Spin-Orbit Torque Neuromorphic Fabrics for Low-Leakage Reconfigurable In-Memory Computation," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1727-1735, April 2022, doi: 10.1109/TED.2021.3140040. [Paper]
[CP: ICECS'21] M. Hossain, S. Salehi, D. Mulvaney, and R. DeMara, "Embedded STT-MRAM Energy Analysis for Intermittent Applications using Mean Standby Duration," 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dubai, United Arab Emirates, 2021, pp. 1-6, doi: 10.1109/ICECS53924.2021.9665581. [Paper]
[CP: GLSVLSI'21] M. Liu, K. Han, S. Luo, M. Pan, M. Hossain, B. Yuan, R. F. DeMara, and Y. Bai, " An efficient video prediction recurrent network using focal loss and decomposed tensor train for imbalance dataset," ACM Great Lakes Symposium on VLSI, Virtual Event, USA, 2021, pp. 391-396, doi: 10.1145/3453688.3461748. [Paper + Presentation]
[E: FIOS'20] R. F. DeMara, S. Silvermann, M. Reddy-Vangala, and M. Hossain, “Imparting Future Workforce Skills using Virtualized Active Learning: A Case Study in an Engineering Core Course,” Florida Online Innovation Summit, Orlando, FL, USA, March 3, 2020. [Paper]
[T: MS Thesis'19] M. Hossain, Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification, NDSU ProQuest Dissertations & Theses, 2019. 22615146. [Thesis]
[CP: ISCAS'19] M. Hossain, A. A. Sakib, S. K. Srinivasan, and S. C. Smith, "An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702098. [Paper]