Monil Mohammad Alaul Haque
Research Scientist, Architecture and Performance Group, Oak Ridge National Laboratory
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Main research focus: Improving HPC runtimes using memory-centric performance models.
Short Bio: I am currently working as a Research Scientist at the Architecture and Performance group, Oak Ridge National Laboratory. I recently finished PhD in Computer Science from University of Oregon, USA. During PhD, I worked with the Future Technology Group of Oak Ridge National Laboratory, USA. My research interest spans multiple domains of High-Performance Computing (HPC), like memory-centric performance modeling, heterogeneous systems, and dynamic adaptation in HPC runtimes. Before starting my PhD at UO, I worked at Grameenphone Ltd - Telenor for 9 years as a lead engineer. I received my MS and BSc degrees respectively from North South University and Khulna University of Engineering & Technology, Bangladesh.
Research Interest in HPC domain
Memory-centric performance modeling
Heterogeneous Systems and runtimes for HPC.
Performance measurement and analysis in HPC environment.
Dynamic adaptation of runtime parameters.
Energy efficient algorithms.
RECENT NEWS:
February - 22: Joined the Architecture and Performance group at Oak Ridge National Laboratory as a Research Scientist
December - 21: Officially graduated from University of Oregon
November - 21: Successfully defended my PhD
July - 21: Citation reached 200 in google scholar.
March- 21: Advanced to candidacy - Passed Area Exam with distinction.
November- 20: Oak ridge national laboratory published an article about my research: https://orise.orau.gov/ornl/experiences/graduate/monil.html
November- 20: Student volunteer at SC for the fourth time.
October - 20: Workshop at SC'20: MCHPC20: My paper: "Understanding the Impact of Memory Access Patterns in Intel Processors" is accepted.
October - 20: Citation reached 150 in google scholar.
July-20 : PACT'20: My paper "MEPHESTO: Modeling Energy-Performance in Heterogeneous SOCs and Their Trade-Offs" has been accepted at PACT'20. Acceptance rate: 26%
September -19: Citation reached 100 in google scholar.
Recent publications
Understanding the Impact of Memory Access Patterns in Intel Processors, MCHPC20 - SC-20
Recent Research
Memory Contention aware kernel collocation for shared memory heterogeneous systems
The objective of my research at ORNL is to study the impact of memory contention on energy and performance in the heterogeneous system on Chips. In recent times, the use of heterogeneous systems on a chip is on the rise. The most interesting fact about this kind of heterogeneous systems is that all the processors share single system memory. So, whenever all the processors want to communicate to the system memory there should be memory access contention, stalling, and delay. As said earlier, the main objection of my current research is to investigate this contention and try to find out a solution to reduce the impact of contention and ensure a better energy and performance outcome.
NVIDIA Xavier SoC
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