Harware Accelerators for AI-based workloads, System Design for Edge Acclerators, Computer Architecture
Ph.D. in Computer Science, Aug 2019 - Sep 2024
Advisor: Prof. Li-Shiuan Peh
M.Sc. (Hons.) in Physics and B.E (Hons.) in Electrical and Electronics Engineering, Aug 2014 - May 2019
SENIOR NPU DESIGN ENGINEER, May 2024 - Present
Working on the design and analysis of an ASIC NPU accelerator architecuture targeting image sensors for edge applications
GRADUATE RESEARCH ASSISTANT (MENTOR: PROF. LI-SHIUAN PEH), Aug 2019 - Sep 2024
Worked on the design and analysis of a dynamic NoC-based acclerator for mixture of expert based neural networks (Under submission)
Worked on the design of NOVA, a NoC-based hardware approximator for the approximation of non-linear functions for attention-based neural networks on CNN accelerator (Paper presented at DATE 2024)
Worked on the design of REACT, an edge accelerator designed using a NoC -based architecture (Paper presented at DAC 2022)
Contributed to tapeout of Shenjing, an SNN-based extremely low power inference accelerator (Paper published at ISCAS 2023 and TVLSI 2024)
RESEARCH INTERN (MENTOR: DR. HARIS JAVAID AND DR. CHENGCHEN HU), May 2020 - July 2020
Worked on the design of hardware-software co-designed model of an endorsement policy evaluator in the Hyperledger Fabric blockchain distributed system on Xilinx Alveo FPGA accelerators for performance improvement (Paper presented at ICDCS 2022)
CO-OP ENGINEER (MENTOR: DR. PRASENJIT BASU AND DR. ANASUA BHOWMIK), Jan 2019 - Jun 2019
As a part of my second undergraduate thesis, worked on HPC workload characterization by benchmarking current state-of-the-art workloads and trAs a part of my undergraduate thesis, worked on the mapping of the KLT Object Tracking Algorithm on Heterogeneous Platform on the Odroid XU-4 board using OpenCL parallel programming to improve the application performanceace models of those on simulator to study effect of vector instructions on next generation processor performance
RESEARCH INTERN (MENTOR: DR. ALOK PRAKASH AND PROF. T. SRIKANTHAN), Jul 2018 - Dec 2018
As a part of my undergraduate thesis, worked on the mapping of the KLT Object Tracking Algorithm on Heterogeneous Platform on the Odroid XU-4 board using OpenCL parallel programming to improve the application performance
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing, Dongrui Li, Ming Ming Wong, Yi Sheng Chong, Jun Zhou, Mohit Upadhyay, Ananta Balaji, Aarthy Mani, Weng Fai Wong, Li Shiuan Peh, Anh Tuan Do, Bo Wang, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, TVLSI 2024
NOVA: NoC-based Vector Unit for Mapping Attention on a CNN Accelerator, Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong and Peh Li-Shiuan, Design, Automation and Test in Europe Conference 2024, DATE 2024
1.7pJ/SOP, 0.5V Scalable Neuromorphic Processor with Integrated Partial Sum Router for In-Network Computing, B. Wang, M. M. Wong, D. Li, Y.S. Chong, J. Zhou, W. F. Wong, L. Peh, A. Mani, M. Upadhyay, A. Balaji, and A. T. Do, ISCAS 2023
Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing, B. Wang, K. Dong, N. Zakaria, M. Upadhyay, W. Wong, and L. Peh, 19th International SoC Conference, ISOCC 2022
REACT: A Heterogeneous Reconfigurable Neural Network Accelerator with Software-Configurable NoCs for Training and Inference on Wearables, Mohit Upadhyay, Rohan Juneja, Wang Bo, Zhou Jun, WengFai Wong, Peh Li-Shiuan, 59th Design Automation Conference, DAC 2022
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric, Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon Brebner, ICDCS 2022
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture, Mohit Upadhyay, Monil Shah, P Veda Bhanu, J Soumya, Linga Reddy Cenkeramaddi, 32nd International Conference on VLSI Design, VLSID 2019
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design, Mohit Upadhyay, Monil Shah, P Veda Bhanu, J Soumya, Linga Reddy Cenkeramaddi, Henning Idsøe, IEEE TENCON 2018
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration, Mohit Upadhyay, Monil Shah, P Veda Bhanu, J Soumya, Linga Reddy Cenkeramaddi, International Conference on High Performance Computing and Simulation, HPCS 2018
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips, Monil Shah, Mohit Upadhyay, P Veda Bhanu, J Soumya, Linga Reddy Cenkeramaddi, 22nd International Symposium on VLSI Design and Test, VDAT 2018
NUS Research Incentive Award: For good academic standing and research progress in graduate studies, 2023
NUS Research Scholarship: To pursue graduate studies at National University of Singapore, 2019
CASS Travel grant: Travel grant to attend Computer Architecture Summer School (CASS) 2018 at IIT Kanpur
Off-Campus Thesis Grant: Travel grant from BITS Pilani for pursuing an off-campus thesis abroad during the final year of undergraduate studies
The 1st NTU-Imperial Workshop on Future Cloud Systems: Presented the poster on NOVA NTU, Singapore at NTU in Jun 2024
Design, Automation and Test in Europe Conference: Gave a talk on the NOVA architecture which was presented at DATE at Valencia, Spain in Mar 2024
Design Automation Conference: Gave a talk on the REACT architecture which was presented at 59th DAC held at San Francisco, USA in Jul 2022
AMD/Xilinx NUS workshop: Gave a talk on the REACT architecture @ NUS, May 2022
Artifact Evaluation Committee Member: MICRO 2023
Sub-reviewer: APCASS 2022, ICCAD 2022, ICCAD 2021
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