Educational Qualification:
Ph.D.
NSIT, (University of Delhi), Delhi
M. Tech in Electronics Engineering
Yeshwatrao Chavan College of Engineering, Nagpur
Bachelor of Electronics Engineering
RTMN University, Nagpur
Area of Specialization: Analog Circuit Designs, Low Power Design Techniques, and Embedded Systems
Teaching Experience : 12 years
Subjects Taught: Microprocessors and Microcontrollers, Digital Circuits, Digital Signal Processing, Electrical Science, Microelectronics
Journal and Conference Publications:
International Journals:
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application, Integration, The VLSI Journal (Elsevier), vol. 84, pp. 47-61, 2022.
Low Voltage High Performance Super Class AB OTA design using SCCM and DTMOS with Enhanced Slew Rate and DC Gain, Microelectronics Journal (Elsevier), vol.113, 2021.
DTMOS Based Low Power Adaptively Biased Fully Differential Transconductance Amplifier with Enhanced Slew-Rate and its Filter Application, IETE Journal of Research (Taylor and Francis), 2021.
Efficient Wide Frequency Range Voltage Control Oscillator for PLL using 180nm CMOS Technology, International Journal of Engineering Research & Technology (IJERT), Volume 4 Issue 06, June 2015.
Study of Tree Multiplier Using Reversible Logic Gate, International Research Journal of Engineering and Technology (IRJET), vol. 02, no 02, May 2015.
Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder, International Journal for Research in Emerging Science and Technology, vol. 2, no. 5, 2015.
International Conferences:
Low Voltage Adaptive Biased OTA with Enhanced Slew Rate and its application in Universal Filter, 5th IEEE International Conference on Electrical,Electronics, Communication, Computer Technologies & Optimization Techniques (ICEECCOT2021), GSSSIETW, Mysuru, India, 10th-11th December 2021.
Low Voltage High Performance Fully Balanced Operational Transconductance Amplifier with Improved Slew Rate, 7th IEEE International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, pp. 819-823, February-2020.
HDL Implementation of 128-Bit Fused Multiply Add Unit for Multi Mode SoC, IEEE International Conference on Communication and Signal Processing (ICCSP’14), Melmaruvathur, Chennai, India, pp. 595-599, April-2014.
FPGA Implementation of 128-Bit Fused Multiply Add Unit for Crypto Processors, International conference on Security in Computing and Communications (SSCC 2015) as book chapter in Communications in Computer and Information Science, vol. 536, Springer.
Outreach Activities:
Attended Two Days FDP on “Essentials of Linux System Administration” organized by Fr. Conceicao Rodrigues College of Engineering, Mumbai, on 16th-17th April 2021.
Participated in AICTE Sponsored One week Online Short Term Training Programme (STTP) on “VLSI Design Using Cadence Tools” organized by Sardar Patel Institute of Technology, Mumbai, from 12th Oct-5th Dec 2020.
Participated in AICTE Sponsored Online Short Term Training Program (STTP) on “Recen Trends & Applications in Analog VLSI Design” organized by Priyadarshini College of Engineering, Nagpur from 26th-31st October 2020.
Attended One Day workshop online Hand-on workshop on Microchip’s Internet of Things in association with Apis solution Bengaluru, organized by department of Electronics and Communication Engineering Shri Venkateshwara College of Engineering, Bengaluru on 14th May 2020.
Attended One week FDP on “Effective Proposal Writing for Research and Funding”organized by Sandip Institute of Technology and Research Center, Nashik in association with IEEE Women in Engineering from 13th-18th May 2020.
Participated in One Week FDP on “Analog Integrated Circuit Design using Cadence Analog Design Flow”, organized by JSS Academy of Technical Education, Noida and sponsored by Dr. A.P.J. Abdul Kalam Technical University, Lucknow under TEQIP Phase-III from 27th August -1st September 2018.
Participated in One Week STTP on “Research Methodology”, organized by Delhi School of Management, Delhi Technological University from 14th-18th December 2016.
Participated One week STTP on “Advanced Embedded System Design using ARM Processor and Lab-View” (AESD-15) approved by ISTE organized by Electronics department YCCE from 14th-18th December 2015.
Participated in Two weeks ISTE Workshop on “Introduction to Research Methodologies” conducted by IIT Bombay from 25th June-04th July 2012 under MHRD.
FDP Organized:
Organized One Week Short Term Course on "Emerging Trends in Electronics and Communication" July 2023 as Co-organizing Secretary
Organized Two days International Conference “Techotronics-17” as Co-organizing Secretary.
Organized Two days International Conference “Techotronics-16” as a co-ordinator.
Organized Two days National workshop on Quad Copter in association with IIT Madras in February 2015. 50 students participated from the Vidarbha Region.
Organized Three days National workshop on “Scilab” sponsored by IIT Mumbai in 2011 for the Faculty and Research Scholars.
Organized Three days National workshop on i-Robotics in association with IIT Bombay in 2011.
Awards/Professional Services:
Received Best Paper Award by 5th IEEE International Conference on Electrical, Electronics, Communication, Computer Technologies & Optimization Techniques (ICEECCOT2021), GSSSIETW, Mysuru, India in 2021.
Life Membership of ISTE and IEI.