Publications

 Journal Papers:

1. Hau Sim Choo, Chia Yee Ooi, Nordinah Ismail, Michiko Inoue, Chee Hoo Kok, "Improving Hardware Trojan Detection Coverage by Utilizing Features at Different Abstraction Levels," Journal of Advanced Research in Applied Sciences and Engineering Technology, vol.32, no.1, pp73 -86, 30 Aug. 2023, doi:10.37934/araset.32.1.7386.

2. Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani, "Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects," IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, IEICE, vol.Advanced publication, 19 Jul. 2023, doi:10.1587/transfun.2023KEP0010.

3. Grégory Bénassy, Fukuhito Ooshita, Michiko Inoue, “Eventually consistent distributed ledger despite degraded atomic broadcast,” Concurrency and Computation: Practice and Experience, vol.35, no.11, ppe6199, 15 May. 2023, doi:10.1002/cpe.6199, naistar.

4. Yuya Isaka, Michihiro Shintani, Foisal Ahmed, Michiko Inoue, "Systematic unsupervised recycled field-programmable gate array detection," IEEE Transactions on Device and Materials Reliability, 22(2), pp.154-163, June 2022.

5. Jion Hirose, Junya Nakamura, Fukuhito Ooshita, Michiko Inoue, "Weakly Byzantine gathering with a strong team," IEICE Transactions on Information and Systems, vol.E105-D, no.3, Mar. 2022.

6. Yuya Isaka, Michihiro Shintani, Michiko Inoue, "Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis," Japanese Journal of Applied Physics, Feb. 2022.

7. Shota Nagahama, Fukuhito Ooshita, Michiko Inoue, "Terminating grid exploration with myopic luminous robots," International Journal of Networking and Computing, Jan. 2022.

8. Hiroto Yasumi, Fukuhito Ooshita, Michiko Inoue, Sebastien Tixeuil, "Uniform Bipartition in the Population Protocol Model with Arbitrary Graphs," Theoretical Computer Science, Sep. 2021.

9. Riaz-ul-haque Mian, Michihiro Shintani and Michiko Inoue. "Hardware–software co-design for decimal multiplication." Computers 10.2 (2021): 17.

10. Foisal Ahmed, Michihiro Shintani and Michiko Inoue, “Accurate recycled FPGA detection using an exhaustive-fingerprinting technique assisted by WID process variation modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Early Access ), 14 Sep. 2020.

11. Foisal Ahmed, Michihiro Shintani, Michiko Inoue, “Cost-efficient Recycled FPGA detection through statistical performance characterization framework,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E103-A, no.9, pp1045-1053, Sept. 2020.

12. Mamoru Ishizaka, Michihiro Shintani and Michiko Inoue, “Area-efficient and reliable error correcting code circuit based on hybrid CMOS/memristor circuit,” Journal of Electronic Testing: Theory and Applications, vol.36, no.4, pp537-546, Aug. 2020.

13. Gian Mayuga, Yasuo Sato, Michiko Inoue, "Highly reliable memory architecture using adaptive combination of proactive aging-aware in-field self-repair and ECC," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.39, no.8, pp1688-1698, 17 Jul. 2020.

14. Masashi Tsuchida, Fukuhito Ooshita and Michiko Inoue, “Byzantine-tolerant gathering of mobile agents in asynchronous arbitrary networks with authenticated whiteboards,” IEICE Transactions on Information and Systems, vol.E103-D, no.7, Jul. 2020.

15. Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail and Chee Hoo Kok, “A review of hardware Trojan detection: An overview of different pre-silicon techniques,” Defence S and T Technical Bulletin, vol.13, no.1, pp1-21, 14 Apr. 2020.

16. Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Chee Hoo Kok, "Register-transfer level features for machine-learning-based hardware Trojan detection," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E103-A, no.2, 1 Feb. 2020

17. Hiroto Yasumi, Fukuhito Ooshita, Ken'ichi Yamaguchi and Michiko Inoue, “Space-optimal population protocols for uniform bipartition under global fairness,” IEICE Transactions on Information and Systems, vol.E102-D, no.3, Mar. 2019.

18. Hiroto Yasumi, Naoki Kitamura, Fukuhito Ooshita, Taisuke Izumi and Michiko Inoue, “A population protocol for uniform k-partition under global fairness ,” IJNC Special Issue on APDCM 2018, Jan. 2019.

19. Masashi Tsuchida, Fukuhito Ooshita, Michiko Inoue, "Byzantine-tolerant Gathering of Mobile Agents in Arbitrary Networks with Authenticated Whiteboards," IEICE Transactions on Information and Systems, Vol.E101-D, No.3, Mar. 2018.

20. Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue, "An integrated DFT solution for power reduction in scan test applications by low power gating scan cell," Integration, the VLSI Journal, Vol.57, pp.108-124, March 2017.

21. Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, "An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan," IEICE Transactions on Information and Systems, Vol.100, No.1, pp. 130-139, Jan. 2017.

22. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue, "Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair," IEICE Transactions on Information and Systems, Vol.99, No.10, pp.2591-2599, Oct. 2016.

23. Yuma Asada, Fukuhito Ooshita, Michiko Inoue, “An Efficient Silent Self-Stabilizing 1-Maximal Matching Algorithm in Anonymous Networks,” Journal of Graph Algorithms and Applications, Vol. 20, No. 1, pp. 59–78, 2016.

24. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, “A Scan-Based On-Line Aging Monitoring Scheme,” Journal of Semiconductor Technology and Science, Vol.14, No.1, February, 2014.

25. Michiko Inoue and Tomokazu Yoneda, "High quality delay test for VLSI field test," the journal of Reliability Engineering Association of Japan, Vol. 35, No. 8, pp.504, Dec. 2013 (In Japanese).

26. Michiko Inoue, Akira Taketani, Tomokazu Yoneda and Hideo Fujiwara, “Test pattern ordering and selection for high quality test set under constraints,” IEICE Trans. on Information and Systems Vol. E95-D, No. 12, pp.3001-3009, Dec. 2012.

27. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara and Hideo Fujiwara, "A failure prediction strategy for transistor aging," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 20, Issue 11, pp.1951 – 1959, Nov 2012.

28. Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara, "Balanced secure scan: partial scan approach for secret information protection," Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, No. 2, pp.99-108, Apr. 2011.

29. Masato Nakazato, Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara, "Design for testability method to avoid error masking of software-based self-test for processors," IEICE Trans. on Information and Systems, Vol. E91-D, No. 3, pp.763-770, Mar. 2008.

30. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Instruction-based self-testing of delay faults in pipelined processors," IEEE Trans. on Very Large Scale Integration (VLSI)Systems, Vol. 14, No. 11, pp.1203-1215, Nov. 2006.

31. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," IEICE Transactions on Information and Systems, Vol. E89-D, No. 6, pp.1931-1939, June 2006.

32. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Non-scan design for single-port-change delay fault testability," IPSJ Journal, Vol. 47, No. 6, pp.1619-1628, June 2006.

33. Zhiqiang You, Ken-ichi Yamaguchi, Jacob Savir, Michiko Inoue and Hideo Fujiwara, "Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths," IEICE Transactions on Information and Systems, Vol. E88-D, No. 8, pp.1940-1947, Aug. 2005.

34. Michiko Inoue, Kazuko Kambe, Virendra Singh and Hideo Fujiwara, "Software-based self-test of processors for stuck-at faults and path delay faults," Trans. of IEICE (DI), Vol. J88-D-I, No. 6, pp.1003-1011, June 2005. (In Japanese) .

35. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Delay fault testing of processor cores in functional mode," IEICE Trans. on Information and Systems, Vol. E88-D, No. 3, pp.610-618, Mar. 2005.

36. Chikateru Jinno, Michiko Inoue and Hideo Fujiwara, "Internally balanced structure with hold and switching functions," Trans. of IEICE (DI), Vol. J86-D-1, No. 9, pp.682-690, Sep. 2003. (In Japanese) .

37. Ken-ichi Yamaguchi, Michiko Inoue and Hideo Fujiwara, "Hierarchical BIST: test-per-clock BIST scheme with low overhead," IEICE Trans. on Information and Systems, Vol. J86-D-1, No. 7, pp.469-479, July 2003. (In Japanese) .

38. Michiko Inoue, Emil Gizdarski and Hideo Fujiwara, "Sequential circuits with combinational test generation complexity under single-fault assumption," Journal of Electronic Testing Theory and Applications, Vol. 18, No. 1, pp.55-62, Feb. 2002.

39. Hirohito Taniguchi, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Clustering algorithms in ad hoc networks," Trans. of IEICE (D1), Vol. J84-D-I, No. 2, pp.127-135, Feb. 2001. (In Japanese) .

40. Hiroyoshi Matsui, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Fault-tolerant and self-stabilizing protocols using an unreliable failure detector," IEICE Transactions on Information and Systems, Vol. E83-D, No. 10, pp.1831-1840, Oct. 2000.

41. Sen Moriya, Katsuro Suda, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Wait-free linearizable distributed shared memory," IEICE Transactions on Information and Systems, Vol. E83-D, No. 8, pp.1611-1621, Aug. 2000.

42. Toshimitsu Masuzawa, Michiko Inoue, "Fault-tolerance of distributed algorithms: Self-stabilization and wait-freedom." IEICE Transactions on Information and Systems, Vol. E83-D, No.3, pp.550-560, March 2000.

43. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Parallel algorithms for the all nearest neighbors of binary image on the BSP model," IEICE Transactions (D), Vol. E83-D, No. 2, pp.151-158, Feb. 2000.

44. Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Optimal wait-free clock synchronization protocol on a shared-memory multi-processor system," Trans. of IEICE(DI), Vol. J83-D-I, No. 1, pp.99-109, Jan. 2000. (In Japanese) .

45. Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa, "Parallel selection algorithms for CGM and BSP models with application to sorting," IPSJ Journal, Vol. 41, No. 5, pp.1500-1508, 2000.

46. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A layout adjustment problem for disjoint rectangles preserving orthogonal order," Trans. of IEICE(DI), Vol. J82-D-I, No. 6, pp.679-690, June 1999. (In Japanese) .

47. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Parallel algorithms for selection on the BSP model and the BSP* model," Trans. of IEICE (DI), Vol. J82-D-I, No. 4, pp.533-542, Apr. 1999. (In Japanese) .

48. Chikara Oohori, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A causal broadcast protocol for disitributed mobile systems," Trans. of IEICE(DI), Vol. J82-D-I, No. 2, pp.425-435, Feb. 1999. (In Japanese) .

49. Takeshi Higashimura, Michiko Inoue and Hideo Fujiwara, "High-level synthesis for weakly testable data paths using design objective extraction," Trans. of IEICE(DI), Vol. J82-D-I, No. 2, pp.401-409, Feb. 1999. (In Japanese).

50. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A cost optimal parallel algorithm for weighted distance transforms," Parallel computing, Vol. 25, No. 4, pp.405-416, 1999.

51. Michiko Inoue, Kenji Noda, Takeshi Higashimura, Toshimitsu Masuzawa and Hideo Fujiwara, "High-level synthesis for weakly testable data paths," IEICE Trans. on Information and Systems (Special Section on Test and Diagnosis of VLSI), Vol. E81-D, No. 7, pp.645-653, July 1998.

52. Michiko Inoue, Toshimitsu Masuzawa and Nobuki Tokura, "Efficient linearizable implementation of shared FIFO queues and general objects on a distributed system," IEICE Trans.on Fundamentals (Special Section on Discrete Mathematics and Its Applications), Vol. E81-A, No. 5, pp.768-775, Mar. 1998.

53. Michiko Inoue and Hideo Fujiwara, "An approach to test synthesis from higher level," INTEGRATION the VLSI journal , Vol. 26, pp.101-116, 1998.

54. Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Non-scan design for testable date paths using thru operation," Trans.of IEICE (DI), Vol. J79-D-I, No. 12, pp.1063-1071, Dec. 1996. (In Japanese) .

55. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A simple parallel algorithm for the medial axis transform," IEICE Trans.on Information and Systems (Special issue on Architecture, Algorithm and Networks for Massively Parallel Computing), Vol. E79-D, No. 8, pp.1038-1045, Aug. 1996.

56. Michiko Inoue, Ken-ichi Hagihara and Nobuki Tokura, "On the bit complexity of the problem of distributed construction of the minimum weight spanning tree in an asynchronous complete network," Trans. of IEICE (DI), Vol. J76-D-I, No. 7, pp.329-338, July 1993. (In Japanese) .

57. Michiko Inoue, Ken-ichi Hagihara and Nobuki Tokura, "On the message complexity of the problem of distributed construction of the minimum weight spanning tree in an asynchronous hypercube network," Trans. of IEICE (DI), Vol. J76-D-I, No. 7, pp.405-406, July 1993. (In Japanese) .

58. Michiko Konoe (maiden name), Ken-ichi Hagihara and Nobuki Tokura, "On the page number of hyper cubes and cube-connected cycles," Trans. of IEICE, Vol. J71-D, No. 3, pp.490-500, 1988. (In Japanese) .

International Conferences:

1. Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani, "Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning," International Test Conference, Anaheim, CA, 11 Oct. 2023.

2. Ryota Eguchi, Fukuhito Ooshita, Michiko Inoue, Sébastien Tixeuil, "Meeting Times of Non-atomic Random Walks," 25th International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2023), SSS 2023, Springer, vol.LNCS 14310, Newjersey, US, 2 Oct. 2023.

3. Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani, "Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects," 28th Asia and South Pacific Design Automation Conference, Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, pp442 -448, Tokyo, 26 Jan. 2023.

4. Jion Hirose, Junya Nakamura, Fukuhito Ooshita, Michiko Inoue, "Gathering despite a linear number of weakly Byzantine agents," 14th International Workshop on Parallel and Distributed Algorithms and Applications, Proceedings of International Symposium on Computing and Networking Workshops (CANDARW), IEEE, Himeji, 21 Nov. 2022.

5. Makoto Eiki, Masuo Kajiyama, Tomoki Nakamura, Michihiro Shintani, Michiko Inoue, "Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data ," International Test Conference, Anaheim, USA, 28 Sep. 2022.

6. Yota Nishitani, Michiko Inoue, Takashi Sato, Michihiro Shintani, "Gate Input Capacitance Characterization for Power MOSFETs Using Turn-on and Turn-off Switching Waveforms," 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe), pp. 1-9, 2022.

7. Jion Hirose, Junya Nakamura, Fukuhito Ooshita, Michiko Inoue, "Brief Announcement: Gathering Despite a Linear Number of Weakly Byzantine Agents," Proceedings of the 2022 ACM Symposium on Principles of Distributed Computing (PODC 2022), pp.375-377, July 2022.

8. Michihiro Shintani, Mamoru Ishizaka, Michiko Inoue, "Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network," IEEE Asian Test Symposium (ATS), pp25-30, 22 Nov. 2021.

9. Michihiro Shintani, Riaz-Ul-Haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, "Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process," IEEE International Test Conference (ITC), pp103-112, 12 Oct. 2021.

10. Foisal Ahmed, Michihiro Shintani, Michiko Inoue, "Study on High-Accuracy and Low-Cost Recycled FPGA Detection," IEEE International Test Conference (ITC), pp133-142, 12 Oct. 2021.

11. Yuya Isaka, Michihiro Shintani, Michiko Inoue, "FPGA Aging Analysis Based on Nearest Neighbor Residual for Unsupervised Recycled Detection," International Conference on Solid State Devices and Materials (SSDM), pp696-697, 6 Sep. 2021.

12. Yuya Isaka, Michihiro Shintani, Foisal Ahmed, Michiko Inoue, "Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation," IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 28 Jun. 2021.

13. Shota Nagahama, Fukuhito Ooshita and Michiko Inoue, "Terminating grid exploration with myopic luminous robots," 23rd Workshop on Advances in Parallel and Distributed Computational Models (APDCM), May 2021.

14. Jion Hirose, Junya Nakamura, Fukuhito Ooshita, and Michiko Inoue, "Gathering with a strong team in weakly Byzantine environments", 22nd International Conference on Distributed Computing and Networking (ICDCN), Jan 2021.

15. Hiroto Yasumi, Fukuhito Ooshita, Michiko Inoue, and Sebastien Tixeuil, "Uniform bipartition in population protocol model with arbitrary communication graphs", 24th International Conference on Principles of Distributed Systems (OPODIS), Dec. 2020.

16. Aoi Ueda, Michihiro Shintani, Michiko Inoue, and Takashi Sato:  “Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation,” in Proc. IEEE Asian Test Symposium (ATS), Nov. 2020.

17. Michihiro Shintani, Tomoki Mino, and Michiko Inoue:  “LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement,” in Proc. IEEE Asian Test Symposium (ATS), Nov. 2020.

18. Jion Hirose, Masashi Tsuchida, Junya Nakamura, Fukuhito Ooshita and Michiko Inoue, “Brief announcement: Gathering with a strong team in weakly Byzantine environments,” 27th International Colloquium on Structural Information and Communication Complexity (SIROCCO), Jun. 2020.

19. Syful Islam, Michihiro Shintani and Michiko Inoue, “ANP: A Self-Reference-Based Random Variation Aware Hardware Trojan Detection Method,” IEEE Workshop on RTL and High Level Testing, 14 Dec. 2019.

20. Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo and Fawnizu Azmadi Hussin, "Net Classification Based on SCOAP and Net Structural Features for Hardware Trojan Detection," IEEE Asian Test Symposium, Dec. 2019.

21. Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok and Fawnizu Azmadi Hussin, "Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level," IEEE Asian Test Symposium, Dec. 2019.

22. Gregory Benassy, Fukuhito Ooshita and Michiko Inoue, “Eventually consistent distributed ledger relying on degraded atomic broadcast,” Proceedings of the 11th International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), Nov. 2019.

23. Shota Nagahama, Fukuhito Ooshita and Michiko Inoue, “Ring exploration of myopic luminous robots with visibility more than one,” Proceedings of the 21st International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS), Oct. 2019.

24. Masashi Tsuchida, Fukuhito Ooshita and Michiko Inoue, “Black hole search despite Byzantine agents,” Proceedings of the 21st International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS), Oct. 2019.

25. Foisal Ahmed, Michihiro Shintani and Michiko Inoue, “Low Cost Recycled FPGA Detection Using Virtual Probe Technique,” IEEE International Test Conference in Asia (ITC-Asia), pp103-108, Sep. 2019.

26. Mian Riaz-ul-haque, Michihiro Shintani and Michiko Inoue, “Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem,” IEEE International System on Chip Conference (SOCC), pp412-417, Sep. 2019.

27. Dafang Zhao, Fukuhito Ooshita and Michiko Inoue, “A Rapid Feasibility Checking for Reconfiguration of Mismatched PV Arrays,” IEEE Photovoltaic Specialists Conference (PVSC), pp1-5, 21 Jun. 2019.

28. Foisal Ahmed, Michihiro Shintani and Michiko Inoue, “Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling,” IEEE European Test Symposium (ETS), 28 May. 2019.

29. Chee Hoo Kok, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo and Michiko Inoue, “Classification of Trojan Nets Based on SCOAP Values using Supervised Learning,” IEEE International Symposium on Circuits and Systems (ISCAS), pp1-5, 28 May. 2019.

30. Michihiro Shintani, Yoshiyuki Nakamura and Michiko Inoue, “Artificial Neural Network Based Test Escape Screening Using Generative Model,” IEEE International Test Conference (ITC), pp9.2, 30 Oct. 2018.

31. Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue and Alex Orailoglu, “Variation-aware Hardware Trojan Detection through Power Side-channel,” IEEE International Test Conference (ITC), ppPHD.4, 29 Oct. 2018.

32. Mian Riaz-ul-haque, Michihiro Shintani and Michiko Inoue, “Decimal Multiplication Using Combination of Software and Hardware,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp239-242, 28 Oct. 2018.

33. Mamoru Ishizaka, Michihiro Shintani and Michiko Inoue, “Area-efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage,” IEEE Asian Test Symposium (ATS), pp167-172, 18 Oct. 2018.

34. Mamoru Ishizaka, Michihiro Shintani and Michiko Inoue, “Area-Efficient Memristor-Crossbar-Based Error Correcting Code Circuit,” Workshop on Security, Reliability, Test, Privacy, Safety and Trust of Future Devices (SURREALIST), 1 Jun. 2018.

35. Hiroto Yasumi, Naoki Kitamura, Fukuhito Ooshita, Taisuke Izumi, Michiko Inoue, “A population protocol for uniform k-partition under global fairness ,” 20th Workshop on Advances in Parallel and Distributed Computational Models(APDCM2018), 2018.5.21.

36. Masashi Tsuchida, Fukuhito Ooshita and Michiko Inoue, “Gathering of Mobile Agents in Asynchronous Byzantine Environments with Authenticated Whiteboards,” The International Conference on Networked systems (NETYS 2018), 7 May. 2018.

37. Michiko Inoue and Sebastien Tixeuil, “Tight Bounds for Universal and Cautious Self-stabilizing 1-Maximal Matching,” The International Conference on Networked systems (NETYS 2018), 7 May. 2018.

38. Hiroto Yasumi, Fukuhito Ooshita, Ken'ichi Yamaguchi and Michiko Inoue, “Constant-space population protocols for uniform bipartition,” Proceedings of the 21st International Conference on Principles of Distributed Systems (OPODIS), Dec. 2017.

39. Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue and Alex Orailoglu, “Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection,” Proceedings of IEEE 26th Asian Test Symposium, pp.49-53, Nov. 2017.

40. Michiko Inoue, Fukuhito Ooshita, Sébastien Tixeuil, "An Efficient Silent Self-stabilizing 1-Maximal Matching Algorithm Under Distributed Daemon for Arbitrary Networks," International Symposium on Stabilization, Safety, and Security of Distributed Systems, pp. 93-108, Nov. 2017.

41. Michiko Inoue, Fukuhito Ooshita, Sébastien Tixeuil, "Brief Announcement: Efficient Self-Stabilizing 1-Maximal Matching Algorithm for Arbitrary Networks," Proceedings of the ACM Symposium on Principles of Distributed Computing, pp. 411-413, July 2017.

42. Fakir Hossain, Tomokazu Yoneda, Michiko Inoue and Alex Orailoglu, “Detecting Hardware Trojans Without A Golden IC Through Clock-Tree Defined Circuit Partitions,” 22nd IEEE European Test Symposium (ETS’17), 22 May. 2017.

43. Masashi Tsuchida, Fukuhito Ooshita and Michiko Inoue, “Byzantine gathering in networks with authenticated whiteboards,” Proceedings of the 11th International Workshop on Algorithms and Computation (WALCOM), Mar. 2017.

44. Michiko Inoue, Fukuhito Ooshita and Sebastien Tixeuil, “An efficient silent self-stabilizing 1-maximal matching algorithm under distributed daemon without global identifiers,” Proceedings of the 18th International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS), Nov. 2016.

45. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue, “Reliability Enhancement of Embedded Memory with Combination of Aging-aware Adaptive In-Field Self-Repair and ECC,” 21th IEEE European Test Symposium (ETS), May. 2016.

46. Fakir Sharif Hossain, Tomokazu Yoneda and Michiko Inoue, “An Effective Scan Segmentation Approach To Detect Hardware Trojan in Integrated Circuits,” IEEE International Women in Engineering Conference on Electrical and Computer Engineering 2015 (WIECON-ECE 2015), Dec. 2015.

47. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue, "An ECC-Based memory architecture with online self-repair capabilities for reliability enhancement,"20th IEEE European Test Symposium (ETS), May 2015.

48. Yuma Asada and Michiko Inoue, "An efficient silent self-stabilizing algorithm for 1-maximal matching in anonymous networks," Workshop on Algorithms and Computation - 2015, Feb. 2015.

49. Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue, "An online repair strategy and reliability for ECC-Based memory architectures," The 15th Workshop on RTL and High Level Testing, Nov. 2014.

50. Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama and Michiko Inoue, “Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units,” IEEE Asian Test Symposium (ATS2014).

51. Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama and Michiko Inoue, "Memory block based scan-BIST architecture for application-dependent FPGA testing," Proc. of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp.85-88, Feb. 2014.

52. Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama and Michiko Inoue, "Efficient scan-based BIST architecture for application-dependent FPGA test," The Fourteenth Workshop on RTL and High Level Testing (WRTLT"13), Dec. 2013.

53. Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satoshi Ohtake, Takumi Hasegawa, Motoyuki Sato and Kotaro Shimamura, "DART: dependable VLSI test architecture and its implementation," International Test Conference, Nov. 2012.

54. Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama and Michiko Inoue, "A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation," International Test Conference, Nov. 2012.

55. Tomokazu Yoneda, Keigo Hori, Michiko Inoue and Hideo Fujiwara, "Faster-than at speed test for increased test quality and in-field reliability," IEEE International Test Conference 2011 (ITC'11), Sep. 2011.        

56. Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara, "Temperature-variation aware test pattern optimization," IEEE European Test Symposium (ETS'11), pp.214, May 2011.

57. Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara, "A test pattern optimization to reduce spatial and temporal temperature variations," IEEE International Workshop on Reliability Aware System Design and Test (RASDAT'11), pp.7-12, Jan. 2011.

58. Tomokazu Yoneda, Michiko Inoue, Akira Taketani and Hideo Fujiwara, "Seed ordering and selection for high quality delay test," IEEE 19th Asian Test Symposium (ATS2010), pp.313-318, Dec. 2010.

59. Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Bipartite full scan design: a DFT method for asynchronous circuits," IEEE 19th Asian Test Symposium (ATS2010), pp.206-211, Dec. 2010.

60. Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang and Hideo Fujiwara, "Capture in turn scan for reduction of test data volume, test application time and test power," IEEE 19th Asian Test Symposium (ATS2010) , pp.371-374, Dec. 2010.

61. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara and Hideo Fujiwara, "Aging test strategy and adaptive test scheduling for soc failure prediction," IEEE International On-Line Testing Symposium (IOLTS'10), pp.21-26, July 2010.

62. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara, "Test pattern selection to optimize delay test quality with a limited size of test set," IEEE European Test Symposium (ETS'10), pp.260, May 2010.

63. Tomokazu Yoneda, Michiko Inoue, Yasuo Sato and Hideo Fujiwara, "Thermal-uniformity aware x-filling to reduce temperature-induced delay variation for accurate at-speed testing," 28th IEEE VLSI Test Symposium (VTS'10), pp.188-193, Apr. 2010.

64. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara, "A method of unsensitizable path identification using high level design information," Conference: International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS2010) , Mar. 2010.

65. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara, "Optimizing delay test quality with a limited size of test set," IEEE International Workshop on Reliability Aware System Design and Test (RASDAT'10), pp.46-51, Jan. 2010.

66. Michiko Inoue, Satoshi Ohtake, Yuichi Uemoto and Hideo Fujiwara, "Path-based resource binding to reduce delay fault test cost," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp.29-32, Nov. 2009.

67. Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang and Hideo Fujiwara, "A response compactor for extended compatibility scan tree construction," IEEE 8th International Conference on ASIC (ASICON2009), pp.609-612, Oct. 2009.

68. Yasuo Sato, Seiji Kajihara, Yukiya Mimura, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A circuit failure prediction mechanism (DART) for high field reliability," Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp.581-584, Oct. 2009.

69. Michiko Inoue, Tsuyoshi Suzuki and Hideo Fujiwara, "Acceleration by contention for shared memory mutual exclusion algorithms," Proceedings of the 23rd International Symposium on Distributed Computing, pp.172-173, Sep. 2009.

70. Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara, "Partial scan approach for secret information protection," Proceedings of the 14th IEEE European Test Symposium (ETS'09), pp.143-148, May 2009.

71. Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara, "Unsensitizable path identification at RTL using high-level synthesis information," 16th IEEE International Test Synthesis Workshop (ITSW 2009), Mar. 2009.

72. Elena Hammari, Michiko Inoue, Einar J. Aas and Hideo Fujiwara, "Delay test of FPGA routing networks by branched test paths," Informal Digest of Papers, 13th IEEE European Test Symposium (ETS'08), May 2008

73. Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability of software-based self-test for processors," 15th IEEE Asian Test Symposium (ATS'06), pp.375-380, Nov. 2006.

74. Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "Extended compatibilities for scan tree construction," IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.75-80, Nov. 2006.

75. Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "Extended compatibilities for scan tree construction," Digest of Papers, 11th IEEE European Test Symposium (ETS'06), pp.13-18, May 2006.

76. Kazuko Kambe, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "Efficient constraint extraction for template-based processor self-test generation," IEEE the 14th Asian Test Symposium (ATS'05), pp.444-447, Dec. 2005.

77. Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "Design for testability based on single-port-change delay testing for data paths," IEEE the 14th Asian Test Symposium (ATS'05), pp.254-259, Dec. 2005.

78. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.184-191, July 2005.

79. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Program-based testing of super-scalar microprocessors," IEEE 14th North Atlantic Test Workshop (NATW'05), pp.79-86, May 2005.

80. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Instruction-based delay fault self-testing of pipelined processor cores," IEEE International Symposium on Circuits and Systems (ISCAS'05), pp.5686-5689, May 2005.

81. Kazuko Kambe, Michiko Inoue and Hideo Fujiwara, "Efficient template generation for instruction-based self-test of processor cores," IEEE 13th Asian Test Symposium (ATS'04), pp.152-157, Nov. 2004.

82. Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir and Hideo Fujiwara, "Power-constrained test scheduling for RTL datapaths of non-scan BIST schemes," IEEE 13th Asian Test Symposium (ATS'04), pp.32-39, Nov. 2004.

83. Michiko Inoue, Kazuko Kambe, Naotaka Hoashi and Hideo Fujiwara, "Instruction-based self-test for sequential modules in processors," IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp.109-114, Nov. 2004.

84. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Instruction-based delay fault self-testing of processor cores," International Conference on VLSI Design 2004, pp.933-938, Jan. 2004.

85. Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "On the non-scan BIST schemes under power constraints for RTL data paths," IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.14-21, Nov. 2003.

86. Hao Wu, Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "Test length minimization under power constraints for combinational circuits," IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.125-127, Nov. 2003.

87. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara, "Test synthesis for datapaths using datapath-controller functions," IEEE the 12th Asian Test Symposium (ATS '03), pp.294-299, Nov. 2003.

88. Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara, "Software-based delay fault testing of processor cores," IEEE the 12th Asian Test Symposium (ATS '03), pp.68-71, Nov. 2003.

89. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara, "Test synthesis for datapaths using datapath-controller functions," Digest of Papers of European Test Workshop (ETW2003), pp.207-208, May 2003.

90. Ken-ichi Yamaguchi, Michiko Inoue and Hideo Fujiwara, "Hierarchical BIST: test-per-clock BIST with low overhead," Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02), pp.42-47, Nov. 2002.

91. Michiko Inoue, Chikateru Jinno and Hideo Fujiwara, "An extended class of sequential circuits with combinational test generation complexity," Proceedings of 2002 IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2002), pp.200-205, Sep. 2002.

92. Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa and Hideo Fujiwara, "Adaptive long-lived o(k^2)-renaming with o(k^2) steps," 15th International Symposium on Distributed Computing (LNCS2180), pp.123-135, 2001. Abstract

93. Michiko Inoue, Emil Gizdarski and Hideo Fujiwara, "A class of sequential circuits with combinational test generation complexity under single-fault assumption," Proceedings of the Ninth Asian Test Symposium (ATS2000), pp.398-403, Dec. 2000.

94. Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa, "Parallelizability of some P-complete problems," Proceedings of, pp.116-122, May 2000.

95. Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara, "A method of test generation for weakly testable data paths using test knowledge extracted from RTL description," IEEE the 8thAsian test symposium (ATS'99), pp.5-12, Nov. 1999.

96. Sen Moriya, Katsuro Suda, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Wait-free linearizable distributed shared memory," Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS'99), pp.335-342, Nov. 1999.

97. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Parallel algorithms for finding all nearest neighbors," Joint Symposium on Parallel Processing, pp.253-260, June 1999. (In Japanese) .

98. Akihiro Fujiwara, Takashi Ishimizu, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Parallel selection algorithms for CGM and BSP with application to sorting,," Joint Symposium on Parallel Processing, pp.261-268, June 1999.

99. Akihiro Fujiwara, Hirokazu Katsuki, Michiko Inoue and Toshimitsu Masuzawa, "Parallel selection algorithms with analysis on clusters," Proceedings of 1999 International Symposium on Parallel Architectures, Algorithm, and Networks I-SPAN'99, pp.388-393, June 1999.

100. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Parallel algorithms for all nearest neighbors of binary images on the BSP model," Proceedings of 1999 International Symposium on Parallel Architectures, Algorithms, and Networks I-SPAN'99, pp.394-399, June 1999.

101. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A layout adjustment algorithm for disjoint rectangles preserving orthogonal order," Sixth Symposium on Graph Drawing (LNCS 1574), pp.183-197, Jan. 1999.

102. Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa and Hideo Fujiwara, "A high-level synthesis method for weakly testable data paths," IEEE the 7th Asian Test Symposium (ATS'98), pp.40-45, Dec. 1998.

103. Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Self-stabilizing wait-free clock synchronization with bounded space," the 2nd International Conference on Principles of Distributed Systems, pp.129-143, Dec. 1998.

104. Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa, "A parallel algorithm for Euclidean distance transforms on the mesh," the 1998 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'98), pp.1726-1733, July 1998.

105. Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa and Hideo Fujiwara, "Optimal wait-free clock synchronization protocol on a shared-memory multi-processor system," the 11th International Workshop on Distributed Algorithms (LNCS 1320), pp.290-304, Sep. 1997.

106. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A parallel algorithm for weighted distance transforms," 11th International Parallel Processing Symposium, pp.407-412, Apr. 1997.

107. Katuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "Non-scan design for testable data paths using thru operation," Asia and South Pacific Design Automation Conference, pp.313-318, Jan. 1997.

108. Yasuro Sato, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A snapshot algorithm for distributed mobile systems," 16th International Conference on Distributed Computing Systems, pp.734-743, 1996.

109. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara, "A simple parallel algorithm for the medial axis transform of binary images," IEEE Second International Conference on Algorithms & Architectures for Parallel Processing, pp.1-8, 1996.

110. Michiko Inoue, Wei Chen, Toshimitsu Masuzawa and Nobuki Tokura, "Linear-time snapshot using multi-writer multi-reader registers," 8th International Workshop on Distributed Algorithms(Lecture Notes in Computer Science 857, Springer-Verlag), Terschelling, The Netherlands, pp.130-140, 1994.