Weekly Updates

Week 13:

• Lecture 28 4/30/2020

  • Added Lab 6 to website

• Lecture 27 4/28/2020

  • Added Lab 5 to website

Week 13:

• Lecture 26 4/23/2020

  • Laptop charger broke..... no progress made before 4/23

  • Researched theory behind Sobel-edge detection implementation on FPGA

• Lecture 25 4/21/2020

  • Added lab 4 to website

Week 12:

• Lecture 24 4/16/2020

  • Wrapped up Labs 2 and 3, began Lab 4

  • Final Project idea: Edge Detection using FPGA

• Lecture 23 4/14/2020

  • Lab 2 and Lab 3 on site and GitHub

Week 11:

• Lecture 22 4/9/2020

  • Textbook exercises and Lab 2 documentation added to site

• Lecture 21 4/7/2020

  • Added Lab 2 documentation to site

  • Added textbook exercises to site

  • Updated GitHub repo

Week 10:

• Lecture 20 4/2/2020

  • Continued working on website and textbook problems

• Lecture 19 3/31/2020

  • Added Lab 1 documentation onto website

  • Did some chapter exercises from textbook

Week 10:

• Lecture 18 3/26/2020

  • Updated GitHub with lab files

• Lecture 17 3/24/2020

  • Went over new structure of the class

  • Edited website

Week 9:

• Spring Break

• No progress made

Week 8:

• Lecture 16 3/12/2020

  • Gone for interview, did not attend class

• Lecture 15 3/10/2020

  • No Class

Week 7:

• Lecture 14 3/5/2020

  • No class

• Lecture 13 3/3/2020

  • No class

Week 6:

• Lecture 12 2/27/2020

  • Reviewed Chapter 11: Data Objects

  • Issue from Lecture 11 was resolved

    • Jumper must be in QSPI the entire time

  • When booting from configuration memory device , hardware manager MUST be closed before power cycling

  • Lab 2 is complete, code runs at startup

• Lecture 11 2/25/2020

  • Generated memory configuration file

    • hexcount.mcs

  • Purpose was to run code from memory

    • Counter must start whenever powered on

  • Issues:

    • Generated the hexcount.mcs file and was able to start the four digit counter by selecting 'Boot from Configuration Memory Device'

    • Power cycled FPGA and code would not run

      • Board had to be reprogrammed at start up

Week 5:

• Lecture 10 2/20/2020

  • Generated files

    • Source files:

      • hexcount.vhd

      • counter.vhd

      • leddec.vhd

    • Constraint files:

      • hexcount.xdc

• Lecture 9 2/18/2020

  • Began Lab 2

Week 4:

• Lecture 8 2/13/2020

  • Introduction to Finite State Machine Design using VHDL

• Lecture 7 2/11/2020

  • Borrowed NEXYS A7 board

  • Completed first part of Lab 1

    • Configured hardware

    • Downloaded FPGA Configuration File 'leddec.bit' to the FPGA

    • Used slider switches 0~3 to select the value of the 4-bit HEX digit

Week 3:

• Lecture 6 2/6/2020

  • Copied leddec.vhd & leddec.xdc files from Githib

  • Modified switch configuration and added documentation to constraint file

  • Synthesized, implemented, and generated bitstream on Vivado

• Lecture 5 2/4/2020

• • Began Lab 1: Seven Second Decoder

Week 2:

• Lecture 4 1/30/2020

  • Covered Chapter 4

    • Concurrent Statements

    • Signal Assignment Operator "<="

    • Concurrent Signal Assignment Statements

    • Conditional Statement "when"

    • Conditional signal assignment implementation of a MUX

    • Downloaded GHDL

• Lecture 3 1/28/2020

• Covered Chapter 3

  • Entity declaration in VHDL

  • VHDL standard libraries

  • Architecture

  • Signal and Variable assignments