Chapter 4: VHDL Programming Paradigm

4.8 Exercises

a)
--entityentity f1 isport ( A, B : in std_logic; F : out std_logic);end f1;-- architecturearchitecture of a_f1 of f1 isbegin F <= ((not A) and B) or A or ((not B) and A);end a_f1;

b)
--entityentity f2 isport ( A, B, C, D : in std_logic; F : out std_logic);end f2;-- architecturearchitecture of b_f2 of f2 is signal A_out, B_out, C_out : std_logic;begin A_out <= (not A) and C and (not D); B_out <= (not B) and C; C_out <= B and C and (not D); F <= A_out or B_out or C_out;end b_f2;

c)
--entityentity f3 isport ( A, B, C, D : in std_logic; F : out std_logic);end f3;-- architecturearchitecture of c_f3 of f3 is signal A_out, B_out, C_out : std_logic;begin A_out <= (not A) or B; B_out <= (not B) or C or (not D); C_out <= (not A) or D; F <= A_out and B_out and C_out;end c_f3;

a)--conditional signal assignment VHDL model--entityentity g1 isport ( A, B, C, D : in std_logic; F : out std_logic);end g1;-- architecturearchitecture of archg of g1 isbegin F <= '1' when (A = '0' and C = '1' and D = '0') else '1' when (B = '0' and C = '1') else '1' when (B = '1' and C = '1' and D = '0') else ''0';end archg;

b)--selected signal assignment VHDL model--entityentity h1 isport ( A, B, C, D : in std_logic; F : out std_logic);end h1;-- architecturearchitecture of archh of h1 isbegin with ((A = '0' or B = '1'') and (B = '0' or C = '1' or D = '0') and (A = '0' or D = '1')); select F <= '1' when '1', '0' when '0', '0' when others;end archh;

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