Embedded Files
3.6 Exercises
Write VHDL entity declarations that describe the following black box diagrams:
a) entity sys1 isport ( a_in1, b_in2, clk, ctrl_int : in std_logic; out_b : out std_logic);end sys1;
b)entity sys2 isport ( input_w, clk : in std_logic; a_data, b_data : in std_logic_vector(7 downto 0); dat_4 : out std_logic_vector(7 downto 0); dat_5 : out std_logic_vector(2 downto 0));end sys2;
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