Embedded Files
VGA
VGA
The Nexys A7 board was programmed to display a bounce ball on a 640 X 480 VGA monitor connected to the VGA interface on the board. Sync and video signals were generated that were consistent with the VGA standard.
The VGA protocol was designed to drive a cathode ray tube (CRT) display in which an electron beam is raster scanned across the screen as shown below.
In each video frame, the beam is scanned across the screen 480 times to create 480 lines of displayable information. Each horizontal line is then divided into 640 pixels of displayable information. Each pixel is defined by a red, green and blue intensity which defines the brightness and the color of that pixel. The display runs at a frame rate of 60 complete frames per second which is fast enough for your eye to see a continuous image rather than a flickering image.
The FPGA generates horizontal and vertical synchronization signals to control the raster scanning of the display. A horizontal (HSYNC) pulse triggers the horizontal scanning of the next line. A VSYNC pulse brings the beam back up to the top of the display (row 0) to begin a new frame. The controller must also supply red, green and 2 blue video signals that describe the intensity of the current pixel. These are analog signals that range between 0V and 0.7V. These are generated on the Nexys A7 board using an 8-bit video signal and a simple resistor based D/A converter shown below.
System timings for 640x480 60 Hz. operation are shown below. The waveform describes both the vertical and horizontal sync signals. Note that the horizontal (line) period contains display time for the 640 pixels Tdisp, the HSYNC pulse Tpw and two blanking periods Tfp and Tbp which allow time for the beam retrace. Similarly the vertical (frame) period contains time for the 480 lines, the VSYNC pulse and extra time for the vertical retrace. The time periods shown in terms of Clks assume a 25 MHz clock.
The vga_sync.vhd module was created to generate the horizontal and vertical sync waveforms and also the pixel row and column addressing.
The ball.vhd module was created to generate the red, green and blue video that will paint the ball on to the VGA display at its current position.
The vga_top.vhd module was created to connect the vga_sync and ball modules together and connect the appropriate signals to the Nexys A7 VGA port.
The design was synthesized, implemented, and a bit stream file was generated using Vivado Design Suite. Unfortunately I was not able to run the code using VGA monitor because COVID19 prevented me from going to the lab.
Implementation Design
Implementation Design
VHDL Design Schematic shown above
VHDL Design Schematic shown above
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