Lab 2 - Four Digit Hex Counter

GitHub

https://github.com/michaeldelcid/dsd/tree/master/Lab2

Introduction

The purpose of this lab is to extend the design in Lab 1 to create a four digit (16-bit) counter that will display its value using all four 7 segment displays.

To accomplish this I had to find a way to drive one display at a time. We can switch displays 0-3 by enabling its common anode AN0 and decoding count(0-3) to drive the cathode lines. Each display is on for a few milliseconds before shifting to the next display. Each digit is illuminated one quarter of the time (60 Hz) and it appear to our eye as if all four displays are continuously illuminated. Timing wave forms for the technique use are shown below.

The counter module from Lab 1 was modified to generate a 16-bit count value using bits 23 - 38 of the binary counter module. A second output (mpx) was created to multiplex the four 7-segment displays using binary counter bits 17-18. The sequence will repeat at a frequency fast enough to eliminate any visual flicker in the 7-segment displays.

The structure for the modified hexcount module is shown below.The mpx output from the counter module drives the dig input of the leddec module. The 2-bit mpx signal is also used to select which 4-bits of the 16-bit count output should be sent to the data input of the leddec module.

Design was synthesized, implemented and bitstream file was generated using Vivado Design Suite. When I downloaded the FPGA configuration (.bit) file directly onto the FPGA, the configuration data was stored in SRAM on the FPGA device. In order to boot from memory, I had to generate a memory configuration file and move the blue MODE jumper on the FPGA from JTAG to QSPI. The results are shown below.

Final remarks:

The hex counter works perfectly but I would like to read the display differently. I would like to read the display from right to left with the MSB in the 1st display. Also I'd like to display decimal numbers instead of hex.