Lab 1 - LED Decoder

GitHub

https://github.com/michaeldelcid/dsd/tree/master/Lab1

Three files were generated using Vivado 2019:

• leddec.vhd (source file)

• leddec.xdc (constraint file)

Introduction

My first FPGA design will be an LED Decoder that will take as input a 4-bit binary word from four of the slide switches and display its value as a HEX digit on one of the seven segment displays. Each of the seven segment displays consists of seven LED segments A through G which share a common anode. I will be using a Digilent Nexys A7-100t FPGA Trainer Board. Shown below is the Common anode 7-segment display.

Different patterns can be created by turning on selected segments. For example, to make the digit '1', I would turn on segments B and C. A positive voltage (logical '1') is applied to the common anode AN. Each segment is turned on by setting the approriate cathode to ground (logical '0'). The four 7-segment displays share the segment cathode lines shown below.

Any of the 7-segment displays can be enabled by setting the appropriate anode high and then driving the segment code on the CA - CG lines. Multiple displays can be used by time multiplexing the AN0-3 signals but for now I will just use one 7-segment display at a time. The way in which the switches, buttons, LEDs, and 7-segment displays are connected to the FPGA is shown below.

In this design I will use switches SW4 & SW 5 to select which 7-segment display to use. I will generate a 4-bit code using slide switches SW0 - SW3. The encoder table is shown below.

Startup display of FPGA after generating bitstream and programming device.

By using switches 4 & 5 I can chose which display is used.

Using switches 0-3 allows me to change the value of the display screen in hex.