Ultra Low-Cost and Robust Data Processing with Stochastic Logic 

SC was introduced in the 1960s as a collection of techniques representing and processing data in the form of random bit-streams. The key advantages of this paradigm are the very simple hardware to implement complex operations (e.g., multiplication using an AND gate) and its ability to gracefully tolerate high noise rates. SC-based designs consistently achieve 50× to 100× reductions in gate count compared to conventional binary designs. SC has the potential to enable the design of fully parallel and scalable hardware implementations. Latency and energy consumption, however, are the limitations. A primary focus of our research is to address SC’s long-time limitations and challenges, unveiling its potential for the next generation of AI systems. This is what we call SC 2.0, an evolution of the SC paradigm with the added benefits of high performance, high accuracy, and energy efficiency. At the application level, we developed novel low-cost and energy-efficient SC designs for different application domains from image and sound processing to convolutional and deep neural networks. 

Deterministic Methods to Stochastic Computing

For the first time, we showed that SC circuits can produce deterministic and completely accurate results if properly structured. We introduced novel methods for accurate computations with SC logic. We introduced four methods for accurate computations with SC logic: clock dividing bit-streams, using bit-streams with relatively prime lengths, rotation of bit-streams, and using LD bit-streams.

Polysynchronous Clocking: Computing with Crappy Clocks

For modern integrated circuits, the global clock distribution network (CDN) is a major bottleneck in terms of design effort, area, and performance. High skew tolerance can mitigate the costs: either the global CDN can be eliminated entirely, or one can design a relaxed CDN. We investigate Polysynchronous Clocking, a design strategy in which clock domains are split at a very fine level, reducing power on an otherwise large global clock tree. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock tree network can be relaxed. This allows for a higher working frequency and so lower latency. Polysynchronous clocking results in significant latency, area, and energy savings for a wide variety of applications including image and signal processing applications. 

In-memory computing (IMC)–aka processing in memory– is introduced as a promising solution to accelerate big data applications by addressing the data movement issue between memory and processing unit and enabling extensive parallelism. IMC with non-volatile memories (NVMs) has shown great potential for in-place computations. However, there are multiple key technical challenges that make it difficult to use IMC as a part of today’s computing systems. The emerging memory devices have various reliability issues such as endurance, durability, and variability. They are prone to soft errors in the logical states. This often causes significant errors in the computation when using the traditional binary representation.

An important focus of our research is to exploit unconventional and alternative computation techniques to develop efficient and robust IMC architectures. SC and UC use a redundant bit-stream representation that can inherently tolerate high rates of noise. Our research combines the complementary advantages of SC/UC and IMC to achieve reliable and fast computation in NVMs. We introduced the first exact SC-based in-memory multiplier. The proposed multiplier can perform fast and accurate multiplication, replacing the conventional binary multiplier. The latency decreases from hundreds of cycles to only a few. We further developed the first architectures for in-memory sorting of data: a binary and a unary sorting design. The latency and energy are significantly reduced compared to prior off-memory CMOS-based sorting designs.