Talks

Talks

• EDA Workshop, Invited talk, "Reliability Exploration of Neural Network Accelerator" (Aug. 2024)

• GB-RADNEXT Workshop 2024, Invited talk, "Muon-induced Soft Errors in FinFET and Planar SRAMs" (June 2024).

• Semiconductor Technology International Conference (CSTIC), Invited talk, "Logic Locking over TFHE for Securing User Data and Algorithms" (Mar. 2024)

• Asia South Pacific Design Automation Conference (ASP-DAC), Tutorial, "Toward Robust Neural Network Computation on Emerging Crossbar-based Hardware and Digital Systems" (Jan. 2024)

• 第2回 QUP Synergy Summit (QSS2), 招待講演, "宇宙線起因ソフトエラーの動向とQASSの活動紹介" (Oct. 26, 2023)

• Technical University of Munich, Seminar talk, "Toward Correct Understanding and Characterization of Cosmic ray-induced Soft Errors" (Oct. 02, 2023)

• J-PARC陽子照射施設検討に関する研究会, 招待講演, "半導体ソフトエラー試験の現状と施設への期待" (July 27, 2023)

• RADNEXT facility webinar, Invited talk, "Terrestrial Cosmic-Ray SEE testing" (Dec. 14, 2022)

• 中間子科学の将来討論会, 招待講演, "ミュオン起因半導体ソフトエラーの評価と課題" (Nov. 10, 2022)

• 情報科学技術フォーラム(FIT), 招待講演, "ビアスイッチFPGA: 65nm CMOS実装とAI向けアーキテクチャ拡張 " (Sep.13, 2022)

• 原子力学会, 招待講演, "ミュオン起因ソフトエラーの測定と課題 " (Sep. 8, 2022)

• 第13回放射線試験勉強会, 招待講演, "地上向けエラーレート評価の課題" (August, 26, 2022)

• International Test Conference in Asia (ITC-Asia), Keynote talk, "Toward Correct Understanding and Characterization of Cosmic Ray-induced Soft Errors " (August 25, 2022)

• International Interconnect Technology Conference (IITC), Invited talk, "Via-switch FPGA with transistor-free programmability" (June 28, 2022)

• RCNP研究会, 招待講演, "ミューオン起因半導体ソフトエラーの測定と課題” (March 24, 2022)

• 電気三学会関西支部，神戸大学工学研究科電気電子工学専攻 共催講演会 招待講演, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA", (Nov. 2021).

• International Conference on Memristive Materials, Device & Systems (MEMRISYS), Plenary talk, "Via-switch FPGA with transistor-free programmability enabling near-memory parallel computation " (Nov. 2021)

• ILC Workshop on Potential ILC Experiments (ILCX), Invited talk, "Applications outside particle physics (soft error)" (Oct. 2021)

• 電子情報通信学会集積回路研究会 招待講演, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications " (April 2021)

• 「J-PARCにおける半導体ソフトエラー研究の展開」研究会, 招待講演, "宇宙線によるソフトエラーとその対策" (Mar. 2021)

• NV-FPGAシンポジウム, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA" (Mar. 2021)

• AVF合同打ち合わせ, 招待講演, "地上環境における中性子起因ソフトエラーの評価と課題" (Mar. 2021)

• Semiconductor Technology International Conference (CSTIC), Invited talk, "Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution" (Mar. 2021)

• 第81回応用物理学会秋季学術講演会, 招待講演, "高エネルギー効率AIコンピューティングを実現するビアスイッチFPGA" (Sep. 2020)

• International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures (ADMS), Keynote talk, "Pursuing Energy-Efficient AI Computation with Densely-Integrated FPGA" (Aug. 2020)

• KAIST, EE Colloquium, "Soft Error: Cosmic Ray Induced Errors in Digital VLSI Systems Threatening our IT-centric Society" (May 2020)

• Asia and South Pacific Design Automation Conference (ASP-DAC), Invited talk, "Soft Error and Its Countermeasures in Terrestrial Environment" (Jan. 2020)  

• Southeast University, Seminar talk, "Near-/Sub-threshold Circuit Design: Opportunities and Challenges" (Dec. 2019)

• Southeast University, Seminar talk, "Via-switch FPGA enabling energy-efficient neural network computation" (Dec. 2019)

• IBM, Seminar talk, "Via-switch FPGA enabling energy-efficient computing " (Nov. 2019)

• 2019年度J-PARC MLF産業利用報告会 講演, "ミュオン起因半導体ソフトエラーの測定と分析" (July 2019)

• 応用物理学会シリコンテクノロジー分科会 招待講演, "宇宙線起因ソフトエラーの測定と解析 " (July 2019)

• Tokyo Institute of Technology, Seminar talk, "Soft Error in SRAM on Ground" (May 2019)

• 電子情報通信学会VLD研究会 招待講演, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA " (May 2019)

• NV-FPGAシンポジウム, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA" (Mar. 2019)

• 第二回QiSSシンポジウム, "宇宙線によるソフトエラー:  社会的インパクトと評価技術 " (Mar. 2019)

• 電子情報通信学会東北支部学術講演会 セミナー講演, "宇宙線によるソフトエラーとその対策" (Oct. 2018)

• IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Invited talk, "Characterizing soft error rates of 65-nm SOTB and bulk SRAMs with muon and neutron beams" (Oct. 2018)

• Nagoya University, Seminar talk, "Soft Error in SRAM on Ground" (Oct. 2018)

• Technical University of Munich, Seminar talk, "Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors" (Sep. 2018)

• IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Invited talk,, "Interconnect Delay Analysis for RRAM Crossbar based FPGA" (July 2018)

• International Conference on Nanoelectronics Strategy (INS), Invited talk, "Via-switch FPGA enabling energy-efficient algorithm-embedded hardware" (May 2018)

• Rebooting Computing 勉強会 セミナー講演, "メモリコンピューティングの新展開" (Apr. 2018)

• National Chiao Tung University, Seminar talk, "MTTF-aware Design Methodology for Adaptive Voltage Scaling" (Apr. 2018)

• 第一回QiSSシンポジウム, "安全・安心なIoT時代に向けて" (Mar. 2018)

• Semiconductor Technology International Conference (CSTIC), Invited talk, "MTTF-aware Design Methodology for Adaptive Voltage Scaling" (Mar. 2018)

• 日立製作所 セミナー講演, "メモリコンピューティングの新展開" (Feb. 2018)

• 電気関係学会関西支部連合大会 招待講演, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発" (Nov. 2017)

• International Conference on ASIC (ASICON), Invited talk, "Toward Real-time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes" (Oct. 2017)

• International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Invited talk , "Soft Error Rate Estimation with TCAD and Machine Learning" (Sep. 2017)

• International Workshop on Cross-layer Resiliency (ICWR), Invited talk, "MTTF Estimation and Extension under PVT Delay Variation" (July 2017)

• IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Tutorial talk, "Near-/Sub-threshold Circuit Design: Opportunities and Challenges" (May 2017)

• IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Invited talk, "Oscillator-based True Random Number Generator Robust to Process and Environmental Variation" (Dec. 2016)

• IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) Invited talk, "Highly-Dense Reconfigurable Architecture with Overlay Via-Switch Crossbar" (Nov. 2016)

• Shanghai Jiao Tong University, Seminar talk, "Energy-Efficient Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch" (Oct. 2016)

• International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Invited talk, "Energy-Efficient Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch" (Oct. 2016)

• Zhejiang University, Seminar talk, "MTTF Estimation and Extension under PVT Delay Variation" (Oct. 2016)

• Chinese University of Hong Kong, Seminar talk, "Energy-Efficient Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch" (Aug. 2016)

• 電子情報通信学会集積回路研究会 招待講演, "超低電圧SRAMのソフトエラー耐性" (Aug. 2016)

• Technical University of Munich, Seminar talk, "Reducing Timing Error Occurrence for MTTF Extension" (July 2016)

• The Munich Workshop on Design Technology Coupling, Keynote talk, "Estimating Device-Parameter Variation using On-chip Sensitivity-Configurable Ring Oscillator" (June 2016)

• Infineon Technologies AG, Seminar talk, "Average and High Time Resolution On-chip Supply Sensors" (June 2016)

• Infineon Technologies AG, Seminar talk, "Extracting Device-Parameter Variations using Sensitivity-Configurable Ring Oscillators" (June 2016)

• Infineon Technologies AG, Seminar talk, "Soft Errors in SRAMs" (June 2016)

• Asia South Pacific Design Automation Conference (ASP-DAC), Invited talk, "Sensor-based timing adaptation: Examining and tuning the health of circuits" (Jan. 2016)

• National Chiao Tung University, Seminar talk, "Soft Error of Low Voltage SRAM" (Oct. 2015)

• IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Invited talk, "Run-Time Performance Adaptation: Opportunities and Challenges," (June 2015)

• Asian Test Symposium (ATS), Invited talk, "Opportunities and Verification Challenges of Run-Time Performance Adaptation" (Nov. 2014)

• IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Invited talk, "Stochastic Verification of Run-time Performance Adaptation with Field Delay Testing" (Nov. 2014)

• IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Invited talk, "Toward Robust Subthreshold Circuit Design -- Variability and Soft Error Perspective --" (Oct. 2014)

• National Chiao Tung University, Seminar talk, "Run-time Performance Adaptation with Field Delay Testing -- How can we verify in design time? -- " (Aug. 2014)

• National Cheng Kung University, Seminar talk, "Run-time Performance Adaptation with Field Delay Testing -- How can we verify in design time? -- " (Aug. 2014)

• National Taiwan University, Seminar talk, "Run-time Performance Adaptation with Field Delay Testing -- How can we verify in design time? -- " (Aug. 2014)

• University of Electronic Science and Technology of China, Seminar talk, "Robust Ultra-Low Voltage VLSI Design -- Manufacturing and Environmental Variability and Soft Error Perspective --" (Oct. 2013)

• International Conference on ASIC (ASICON), Invited talk, "Soft Error Immunity of Subthreshold SRAM" (Oct. 2013)

• International Test Conference (ITC), Elevator Talk, "Reliability Challenge for Exa-scale Near-threshold Computing -- Soft Error Perspective --" (Sep. 2013)

• Fudan University, Seminar talk, "Run-time VLSI Performance Adaptation and Soft Error Measurement" (Mar. 2013)

• Shanghai Jiao Tong University, Seminar talk, "Reliability-aware coarse-grained reconfigurable architecture and on-chip true random number generator" (Mar. 2013)

• China Semiconductor Technology International Conference (CSTIC), Seminar talk, "Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability" (Mar. 2013)

• International Test Conference (ITC), Elevator Talk, "Adaptive Speed Control and Its Extremely-Low Error Rate Estimation" (Nov. 2012)

• センサマイクロマシンとその応用シンポジウム 招待講演, "低電圧VLSI回路設計" (Oct. 2012)

• 電子情報通信学会 デザインガイア 招待講演, "超低電圧サブスレショルド回路設計" (Nov. 2011)

• EDS Fair 2011 招待講演, "国際学会の技術トレンド 物理設計編" (Nov. 2011)

• Vanderbilt University, Seminar talk, "Introduction of research activities at Osaka University" (Nov. 2011)

• University of Texas at Austin, Seminar talk, "Adaptive Performance Compensation with On-Chip Variation Monitoring" (Sep. 2011)

• Freescale, Seminar talk, "Adaptive Performance Compensation with On-Chip Variation Monitoring" (Sep. 2011)

• ARM, Seminar talk, "Adaptive Performance Compensation with On-Chip Variation Monitoring" (Sep. 2011)

• IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Invited talk, "Adaptive Performance Compensation with On-Chip Variation Monitoring" (Aug. 2011)

• University of Michigan, Seminar talk, "Run-time adaptive performance control and design issues in subthreshold SRAM" (May 2011)

• IBM, Seminar talk, "Adaptive Performance Compensation with On-Chip Variation Monitoring" (Apr. 2011)

• 電子情報通信学会総合大会 チュートリアル講演, "超低電圧サブスレショルド回路設計" (Mar. 2011)

• IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Invited talk, "Run-Time Adaptive Performance Compensation using On-chip Sensors" (Jan. 2011)

• IBM, Seminar talk, "Device-Parameter Estimation with On-chip Variation Sensors Considering Random Variability Toward Performance Self-Compensation" (Oct. 2010)

• Stanford University, Seminar talk, "Introduction of activities in Osaka University" (Aug. 2010)

• エレクトロニクス実装学会 システムJisso-CAD/CAE研究会公開研究会, "製造・環境ばらつきを考慮した統計的静的タイミング解析" (June 2010)

• NTU-Waseda Joint Workshop 2010, Invited talk, "Robust Subthreshold Circuit Design to Manufacturing and Enviromental Variability" (Jan. 2010)

• Cadence Design Systems, Seminar talk, "Static timing analysis with a unified approach to manufacturing and environmental variability" (Sep. 2009)

• IBM, Seminar talk, "On-chip measurement of dynamic power supply noise and noise-aware statistical timing analysis" (Mar. 2009)

• Intel, Seminar talk, "On-chip noise measurement -- inductive coupling noise and dynamic power supply noise --" (Apr. 2008)

• システムLSIワークショップ 招待講演, "オンチップノイズ観測" (Nov. 2007)

• University of California at San Diego, Seminar talk, "On-chip noise measurement -- inductive coupling noise and dynamic power supply noise --" (Nov. 2007)

• 電子情報通信学会 VLSI設計技術研究会 招待講演," 製造・環境ばらつきを考慮したタイミング検証技術" (Oct. 2007)

• 日本情報技術センター セミナー講演, "VLSIチップ内におけるノイズとばらつき対策設計技術" (Sep. 2007)

• 第24回STARC アドバンスト講座 システムアーキテクチャセミナー, "オンチップ伝送線路を利用した高速信号伝送" (July 2007)

• 軽井沢ワークショップ 招待講演, "製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて" (Apr. 2007)

• Extreme-DA, Seminar talk, "A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental Variability," (Nov. 2006)

• 日本情報技術センター セミナー講演, "高性能LSIにおけるオンチップノイズ特性と設計への応用 ～微細、低電圧、複雑化に向けた設計アプローチ" (June 2006)

• University of California at San Diego, Seminar talk, "Performance prediciton of on-chip global signaling" (Mar. 2006)

• ソニー LSI Design 講演, "ゲートレベル遅延／クロストーク計算方法" (July 2005)

• Sequence Design, Seminar talk, "Timing and PG grid analysis for nano-meter technologies," (Apr. 2005)

• Cadence Design Systems, Seminar talk, "Timing and PG grid analysis for nano-meter technologies" (Mar. 2005)

• ソニー 講演, "ゲートレベル遅延／クロストーク計算方法" (Mar. 2005)

• 岡山大学 セミナー講演, "On-chip Global Signaling by Wave-Pipelining" (Jan. 2005)

• システムLSIワークショップ 招待講演, "ナノメートル世代のタイミング解析 -- 信号線・電源線ノイズ、ばらつき、熱への対応 --" (Nov. 2004)

• IEEE Electrical Design of Advanced Packaging and Systems, Invited talk, "Performance Prediction of On-chip Global Signaling" (Nov. 2004)

• Stanford University, Seminar talk, "On-chip Global Signaling by Wave-Pipelining" (Oct. 2004)

• 電子情報通信学会 ソサイエティ大会 チュートリアル講演, "微細LSIにおけるタイミング解析 -電源ノイズ・信号線ノイズ・ばらつきへの対応-" (Sep. 2004)

• University of California at San Diego, Seminar talk, "Design Techniques for High-Performance Circuits in Cell-base Design Framework" (June 2004)

• University of California at Santa Barbara, Seminar talk, "Techniques for crosstalk and inductance aware timing analysis" (Nov. 2003)

• 情報処理学会関西支部VLSIシステム研究会 招待講演, "LSI物理設計におけるSignal Integrity 問題" (Mar. 2003)

Panel moderator

• 1st JST International Symposium on Dependable VLSI Systems 2012 "Toward Cross-Layer Optimization for Dependable Systems" (Dec. 2012)

Panel panelist

• DATE, Focus Session, "Panel On Resilience Of Deep Learning Applications: Where We Are And Where We Want To Go" (Mar. 2024)

• TAU Workshop, "What's the Next Big Timing Signoff Challenge? " (Mar. 2014)

• Electronic Design and Solution Fair "システムLSI設計の今後 ～22nm時代に向けて～" (Jan. 2011)

• VLSI Symposia Joint Ramp Session, "Variability Has Stopped Scaling: Who Will Conquer the Issues of Variability?" (June 2005)

Session chair in international conferences

• Special Session: Radiation Effects, Test, and Fault Tolerance, ATS, 2022.

• Keynote Session, MWSCAS, 2022.

• Keynote Session, MWSCAS, 2022.

• Keynote Session II, ASP-DAC, 2022.

• Session 3C: ML-based Low-Power Architecture, ISLPED, 2020.

• Session 9A: Resilience in Integrated Systems, ASP-DAC, 2020. 

• Joint Focus Session 2: IoT & Sensor, Symposium on VLSI Circuits, 2019.

• Short course 3: Opportunities and Challenges at the Intersection of Security and AI, Symposium on VLSI Circuits, 2019.

• Session 8: Power Distribution Networks, SPI, 2019.

• Session C4: Machine Learning Processors, Symposium on VLSI Circuits, 2018.

• Session 4D: Design for Manufacturability and Reliability, ASP-DAC 2018.

• Session 26: Processors and SoC, Symposium on VLSI Circuits, 2017.

• Special Session 7S: When Backend Meets Frontend: Cross-Layer Design & Optimization for System Robustness, ASP-DAC 2017.

• Session 1A: Fault Injection and Monitoring, PRDC, 2015

• Session 1B: Toward Power Efficient Design, ASP-DAC 2015.

• Session 7: Tackling Timing and Power During Test, ITC, 2014

• Session 8: Singal Processing, Symposium on VLSI Circuits, 2014.

• Session IV: Session C, CSTIC 2013.

• Session 4C: Timing and Power Driven Design Flow, ASP-DAC 2013.

• Session 7B: Timing, Thermal, and Power Issues in High-Performance Design, ASP-DAC 2012.

• Session: Invited Presentation, TAU 2012

• Session 10A: Advanced Timing and Power Optimizations in Physical Design, ICCAD 2011

• Session V: Living with Process Variation, TAU 2011.

• Session 8A: DFM1: Patterning and Physical Design, ASP-DAC 2010.

• Session 7B: Power Optimization and Estimation in the DSM Era, ASP-DAC 2010.

• Session 4B: Analytical Advances in Physical Synthesis, ICCAD 2009.

• Session 2B: Power Analysis and Optimization, ASP-DAC 2009.

• Session 2A: Physical Synthesis and Optimization, ICCAD 2008.

• Session 12: Variation-aware Design, DAC 2008.

• Session 2A: Robust SRAM and Analog Circuits, ISQED 2008.

• Session 4A: Variability Issues in Timing, ASP-DAC 2008.

• Session 29: Bridging the Gap with Silicon, DAC 2007.

• Session 6A: Timing Modeling and Optimization, ASP-DAC 2007.

• Session 7A: Advanced Methods for Leakage Reduction, ASP-DAC 2007.

• Session 7D: Thermal Analysis for the Nano Scale, ICCAD 2006.

• Session TPM2-2: RF Circuits 1, ITC-CSCC 2006.

• Session 10B: Crosstalk Noise Analysis, ASP-DAC 2004.

• Poster Session 3: Logic Level Design/Physical Design II, SASIMI 2003.

• Session 1B: DSM Interconnect and Gate Issues, ASP-DAC 2003.

Session chair in domestic conferences

• セッション2A 招待講演, DAシンポジウム 2019.

• セッション13A 信頼性2, DAシンポジウム 2018.

• セッション3B: 信頼性1, DAシンポジウム 2015.

• インターコネクト技術（1）, 電子情報通信学会 ICD研究会 2014/11.

• セッション3A: ばらつき２, DAシンポジウム 2014.

• 電子情報通信学会 VLD研究会 2013/3.

• セッション4A: 遅延解析, DAシンポジウム 2009.

• セッションC1-2: DFM, 軽井沢ワークショップ 2009

• セッション6B：電源解析／最適化, DAシンポジウム 2008

• セッション2B: 統計的遅延解析, DAシンポジウム 2007

• セッションA2-3: DFM(2), 軽井沢ワークショップ 2007

• セッションA-3: VLSI設計技術, 電子情報通信学会ソサイエティ大会 2006

• 電子情報通信学会 VLD/ICD合同研究会 2006/3

• セッションC-1：レイアウト一般（1）, DAシンポジウム 2004

• セッションSA2-5: 回路の数値解析(2), 軽井沢ワークショップ 2004

• セッションA-3: VLSI設計技術, 電子情報通信学会ソサイエティ大会 2003

• セッションA-9: ディープサブミクロン関連技術, DAシンポジウム 2003

• セッションSC1-3: ハードウェア設計, 軽井沢ワークショップ 2003

• 電子情報通信学会 VLD/ICD合同研究会 2003/3

• 電子情報通信学会 デザインガイア(VLD/ICD/DC) 2002/11

• セッションA-10: ディープサブミクロン関連技術, DAシンポジウム 2002

• セッションC2-4: 性能指向設計, 軽井沢ワークショップ 2002

• 電子情報通信学会 VLD/ICD合同研究会 2002/3