Dept. of Electronics and Communication Engineering
Bharati Vidyapeeth's College of engineering, New Delhi
Email ID: manojsharma@bharatividyapeeth.edu
Office Phone: (011) 25258637, 25278443 Ext.: 303
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STC/ Projectathon/Digital Circuit Design- Synthesis/Layout Design
STC/ Projectathon/Digital Circuit Design- Synthesis/Layout Design
The course "FPGA Programming using Python" is designed for both students and faculty members. The proposed STC aims to provide hands-on exposure to modern FPGA-based system design using high-level programming (Python/PYNQ),
Projectathon synthesis / layout design
Students need to Register using the following link:
February 2026 to April 2026
March 2025 to May 2025
August 2024 to December 2024:
August 2023 to December 2023
Students need to go through the steps as given in the file and videos below. After comprehensively covering the process, attempt the layout problem assigned.
Evaluation would be done as per schedule provided
Help Material is as under:
Approach
Approach
Skills
Skills
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