Objective: The project aimed to develop a system capable of supporting unidirectional serial and parallel data communication, with a selectable mode to determine which communication method will be used. This system was then integrated with a game console, providing two communication modes: Normal Mode and Gaming Mode. In Normal Mode (or Navigation Mode), serial data communication is used, while in Gaming Mode, parallel data communication is employed to achieve faster data transfer at a lower clock frequency, optimizing performance for gaming applications.

After developing and implementing the system using Verilog, we performed the full Place and Route (PnR) flow, successfully completing the project as a full-chip design.

Note: No STA analysis and sign-off checks were performed for this project; the focus was on verifying the results obtained directly from the PnR flow.

Tool used: Technology Node: 45nm

• RTL and testbench - ModelSim and Xilinx Vivado.

• Synthesis - Cadence Genus.

• Placement and Route - Cadence Innovus

HDL used: Verilog and Verilog Testbench.

Figure: Visual representation of start to end process.

Abstract: This project focuses on the full-chip design of a unidirectional USB transmitter using both serial and parallel data communication modes. The chip's functionality is specifically tailored to handle input and output tasks via distinct communication methods. Input signals include a clock, reset, and control bits, which are processed to generate corresponding parallel or serial output data streams. The design process involved detailed I/O pin planning, finite state machine (FSM) design, and flow optimization. Verification was conducted using Verilog testbench code on ModelSim, and the final chip schematic was synthesized and optimized through Cadence Genus and Innovus tools. The design underwent several stages of optimization, including clock tree synthesis (CTS) and physical verification(we just check the report from Innovus and tried to optimize the issues that occurred in PnR stage), with the final results showing minimal violations. This work demonstrates a robust approach to USB transmitter (we are defining this project as USB controller) design, balancing functional requirements with hardware constraints to achieve an efficient implementation.

Figure: FSM diagram.

Methodology: 

• Design Specification and Requirement Analysis.

• I/O Pin Planning and IO PAD implementation.

• Finite State Machine (FSM) Design.

• RTL Design with verilog. (ModelSim)

• Verification using Verilog. Testbench (ModelSim & Xilinx vivado) 

• Physical Design and Optimization. (Cadence Innovus)

• Physical Verification. (Cadence Innovus built in system)

Figure: RTL to block level representation using Xilinx Vivado.

Figure: RTL functionality verification with verilog testbench and it's waveform.

Figure: RTL functionality Cross verification from Xilinx Vivado.

Figure: Schematic diagram after RTL synthesis using Cadence Genus.

Figure: Final result summary and constrains that we applied.

Learnings:

• Gained hands-on experience in designing and analyzing FSM (Finite State Machine) diagrams.

• Improved proficiency in Verilog along with developing and verifying designs using Verilog testbenches.

• Understood the synthesis flow, including RTL-to-gate-level conversion steps.

• Learned the basics of placement and routing (PnR) using GUI-based EDA tools.

• Basic idea of Input files of PnR. (SDC, LEF, LIB,DEF) 

• GDS extraction from Innovus and reopen it from virtuoso.

Difficulties Faced:

• During verification of the Verilog design with the testbench in serial communication mode, we observed that data transfer required at least 8 clock cycles, since the serial communication was implemented using an 8-bit register. This required fine-tuning of the input signal pulse width to ensure correct output behavior. Through this, we gained practical understanding of timing budgeting.

• While integrating I/O PADs, we initially faced difficulties because we were only familiar with conventional Verilog design. With guidance from our respected faculty members, we were able to successfully implement the I/O PADs and complete the top-level design.

My Role in This Project:

• I served as the Team Lead for this project. The core idea of developing a data communication system with both serial and parallel communication modes originated from me. I designed the FSM architecture and developed the Verilog code along with the testbench for functional verification.

• Additionally, I was responsible for the entire Placement and Routing (PnR) stage and ensured smooth coordination within the team. I closely monitored progress, collaborated actively with teammates, and guided technical decisions throughout the project.

Finally, we successfully completed the full-chip implementation, and our project was recognized as the best project of the section.