Mamunar Rahoman

Project Title: RTL Design, functional verification of Serial to parallel and Parallel to serial data communication system using verilog.

Project duration: Undergraduate, Semester break

Objective: The objective of this project is to design and implement a register-based (8-bit) serial to parallel and parallel to serial data communication system using Verilog, along with performing its functional verification to ensure accurate data transmission and reliable system behavior.

Tool used: Xilinx Vivado

Figure: Block representation of serial and parallel data communication system between one IC to another IC.

Background Theory: SerDes is a functional block that Serializes and Deserializes digital data used in high-speed chip-to- chip communication. Modern SoCs for high-performance computing (HPC), artificial intelligence (AI), automotive, mobile, and Internet-of-Things (IoT) applications implement SerDes that can support multiple data rates and standards like PCI Express (PCIe), MIPI, Ethernet, USB, USR/XSR

Implementation of parallel to serial data communication system (Serializer):

Figure: RTL to block level representation of parallel to serial data communication system.

Figure: Functional verification of parallel to serial data communication system using verilog testbench.

Implementation of serial to parallel data communication system (Desrializer):

Figure: RTL to block level representation of serial to parallel data communication system.

Figure: Functional verification of serial to parallel data communication system using verilog testbench.

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