Project Title: 28-Transistor-based CMOS Full-Adder using only Metal-1 to keep other metal layers available for further implementation as an instance.

Project duration: Undergraduate, 4th Year 1st semester VLSI-I theory course assignment.

Objective: The objective of this project is to design and implement a 28-transistor (28T) mirror full adder, followed by performing transistor sizing to achieve proper rise and fall time equalization, ensuring optimized performance and balanced signal transitions. The project was implemented using only Metal-1 routing, ensuring that all higher metal layers remain available for future block-level integration and hierarchical layout expansion. This approach helps maintain design flexibility and supports efficient routing in larger VLSI system implementations.

Tool used: Cadence Virtuoso.