Project duration: Undergraduate, 4th Year 1st Semester
Objective: The main objective of this project was to design and implement a low-transistor full-adder circuit to achieve optimized power consumption, reduced area, and minimized propagation delay. Through this project, I aimed to strengthen my proficiency in VLSI design using Cadence Virtuoso. The work involved implementing the schematic in Virtuoso, analyzing the output waveform for various input patterns, evaluating input–output transfer characteristics, observing average power consumption, and calculating propagation delay at the highest operating frequency as instructed by the faculty.
Tool used: Schematic and Layout - Cadence Virtuoso, Technology Node: 90nm
Figure: Visual representation of start to end process.
Abstract: This project implements a low-power multiplexer-based 1-bit full adder circuit (MBA-12T) inspired by a published research design. The MBA-12T structure uses 12 transistors and leverages reduced transition activity along with charge recycling to minimize short-circuit power consumption. According to the referenced study, this design achieves 26% lower power than conventional 28-transistor CMOS adders, 23% lower power than other 10-transistor adders, and operates 64% faster. This project explores the structure, behavior, and implementation potential of MBA-12T, demonstrating its suitability for low-power, high-speed VLSI applications.
Methodology: The referenced paper proposed and simulated the MBA-12T, a low-power multiplexer-based 1-bit full adder constructed using six identical multiplexers and a total of 12 transistors. The authors evaluated the design using HSPICE simulations, comparing its performance with five existing adders, including the 28-transistor CMOS adder, SERF adder, and other 10-transistor adders. A comprehensive input pattern was applied to cover all possible transitions of a 1-bit full adder. The simulations were performed using 0.35 µm CMOS technology with a 3.3 V supply voltage.
In our project implementation, we observed that the output waveform of the MBA-12T exhibited slight distortion(as used 1V VDD supply), making it difficult to sample accurate sum and carry outputs. To address this issue, we inserted buffer stages at both the Sum and Carry outputs. The addition of these buffers significantly improved the waveform shape, enhanced signal stability, and also contributed to improvements in propagation delay and power consumption during our test evaluations.
Figure: Schematic diagram of MBA-12T with cascaded buffer version.
Figure: Waveform (Input, Output, Avg. power) of MBA-12 with cascaded buffer version.
Figure: Result comparison of MBA-12 and 10T based full adder with cascaded buffer version.
Learnings:
Became proficient in Cadence Virtuoso and gained hands-on experience with multi-corner analysis of CMOS circuits (FF, SS, FS, SF, TT).
Learned that adding a buffer does not always increase delay; in some cases, it can actually reduce propagation delay by strengthening the signal.
Difficulties Faced: In the reference paper, the supply voltage was 3.3 V, whereas in our implementation we used 1 V. This caused distorted output waveforms. To address this issue, we implemented a cascaded buffer version of the MBA-12T. Additionally, we added buffers at the output of a 10T-based full adder for comparison. These modifications improved the signal integrity and allowed for a proper evaluation of propagation delay and power consumption.
My Role in This Project: I approached this project with a goal of learning the complete design and implementation process independently. Following this method, I implemented and tested all the reference circuits on my own before dividing tasks among my teammates. Additionally, the solution of adding buffers at the output points to improve signal integrity was proposed and implemented by me.