As a Teaching Assistant in Minia University I mentored a graduation (capstone) project and we published one paper.

• Mahmoud. H. Kamel, Z. K. Mahmoud, S. W. Elshaeer, R. Mohamed, A. Hassan and A. I. A. Galal, "Comparative Design of NMOS and PMOS Capacitor-less Low Dropout Voltage Regulators (LDOs) Suited for SoC Applications," 2019 36th National Radio Science Conference (NRSC), Port Said, Egypt, 2019, pp. 305-314.

In this paper, two architectures of Low Dropout Voltage Regulator (LDO) using NMOS and PMOS pass transistors is designed and implemented using 130nm CMOS technology. The performance of the two designs is compared while using the same quiescent current, input voltage, output voltage, and compensation capacitors. The two architectures can provide output voltage of 1V from a 1.2V supply voltage and support output current from 30μA to 100mA while consuming a quiescent current of 6μA. Both LDOs can support a range of loading capacitor 0–50pF. The NMOS LDO is designed with an auxiliary charge pump (CP) to step up input voltage of 1.2V to 2V, thus three architectures of CPs are discussed, designed, and optimized to provide a stable 5μA using a 1MHz of switching frequency. The cross-coupled CP is chosen to be the auxiliary CP because it consumed the smallest silicon area. Both LDOs are fully integrated and consume low power so that it can be used in SoCs. The PVT simulations are implemented to ensure the reliability of the design, also the specifications are compared to other techniques reported previously.

During my Master degree I managed to publish two papers

• Mahmoud. H. Kamel, A. N. Mohieldin, E. Hasaneen and H. F. A. Hamed, "A hybrid NMOS/PMOS low-dropout regulator with fast transient response for SoC applications," 2017 29th International Conference on Microelectronics (ICM), Beirut, 2017, pp. 1-4.

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is designed in UMC 130 nm CMOS technology and is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time s 500 nsec. The LDO can supply current from 10 μA to 100 mA consuming quiescent current of 23.7 μA and 83.5 μA, respectively. The performance of the proposed technique is compared with other reported techniques and gives a better performance. It can support load capacitance from 0-50 pF with phase margin that increases from 47° at low load (10 μA) to 80° at high load (100 mA) and power supply rejection ratio (PSRR) less than -9 dB up to 1 MHz.

• Mahmoud H. Kamel, Ahmed N. Mohieldin, El-Sayed Hasaneen, Hesham F.A. Hamed, "A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications", AEU - International Journal of Electronics and Communications, Volume 96, 2018, Pages 207-218, ISSN 1434-8411.

In this paper, a new architecture of a fully integrated low-dropout voltage regulator(LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio(PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm2. Post layout simulations show better performance compared with other reported techniques.