Publications

Journals (22):

1. M. Rathor, A. Sengupta, "Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-aided Trojan Attack", IEEE Embedded Systems Letters (ESL), 2023, doi: 10.1109/LES.2023.3327793.

2. M. Rathor, A. Anshul , A. Sengupta,  "Securing Reusable IP Cores using Voice Biometric based Watermark," IEEE Transactions on Dependable and Secure Computing, Accepted, 2023, doi: 10.1109/TDSC.2023.3315780.

3. M. Rathor and G. P. Rathor, "Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature," IEEE Design & Test, Aug 2023, doi: 10.1109/MDAT.2023.3307576.

4. A. Sengupta, R. Chaurasia, M. Rathor, "HLS based Swarm Intelligence Driven Optimized Hardware IP Core for Linear Regression based Machine Learning", IET Journal of Engineering, Vol. 2023, issue: 8, Aug 2023.

5. A. Sengupta, M. Rathor, R. Chaurasia "Biometrics for Hardware Security and Trust: Discussion and Analysis", IEEE IT Professionals (ITPro), vol. 25, no. 4, pp. 36-44, July-Aug. 2023, doi: 10.1109/MITP.2023.3277594.

6. M. Rathor, A. Sengupta, R. Chaurasia, A. Anshul "Exploring Handwritten Signature Image Features for Hardware Security", IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 20, no. 5, pp. 3687-3698, 1 Sept.-Oct. 2023, doi: 10.1109/TDSC.2022.3218506.

7. M. Rathor, A. Anshul, K Bharath, R. Chaurasia , A. Sengupta, "Quadruple Phase Watermarking during High Level Synthesis for Securing Reusable Hardware IP Cores", Elsevier Journal on Computers and Electrical Engineering, Volume 105, 2023, 108476, ISSN 0045-7906, https://doi.org/10.1016/j.compeleceng.2022.108476.

8. A. Sengupta, M. Rathor, “Facial Biometric for Securing Hardware Accelerators,” IEEE Transactions on Very Large Scale Integration (VLSI), 2020, vol. 29, no. 1, pp. 112-123, 2021, doi: 10.1109/TVLSI.2020.3029245.

9. M. Rathor and A. Sengupta, “IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems,” IEEE Transactions on Consumer Electronics, vol. 66, no. 3, pp. 251-260, Aug. 2020.

10. A. Sengupta and M. Rathor, “Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems”, IEEE Transactions on Consumer Electronics, vol. 66, no. 2, May 2020, pp. 163-172.

11. A. Sengupta and M. Rathor, “Obfuscated Hardware Accelerators for Image Processing Filters-Application Specific and Functionally Reconfigurable Processors,” IEEE Transactions on Consumer Electronics, vol. 66, no. 4, pp. 386-395, Nov. 2020.

12. A. Sengupta, M. Rathor, “Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting”,  IEEE Transactions on Very Large Scale Integration (VLSI), vol. 28, no. 9, pp. 1979-1992, Sept. 2020.

13. A. Sengupta and M. Rathor, “Structural Obfuscation and Crypto-Steganography based Secured JPEG Compression Hardware for Medical Imaging Systems”, IEEE Access, vol. 8, pp. 6543-6565, 2020.

14. M. Rathor, A. Sengupta, “Design Flow of Secured N-Point DFT Application Specific Processor Using Obfuscation and Steganography,” IEEE Letters of the Computer Society, vol. 3, no. 1, pp. 13-16, 1 Jan.-June 2020.

15. A. Sengupta, M. Rathor, S Patil, NG Harishchandra, “Securing Hardware Accelerators Using Multi-Key Based Structural Obfuscation,” IEEE Letters of the Computer Society, vol. 3, no. 1, pp. 21-24, 1 Jan.-June 2020.

16. A. Sengupta, M. Rathor, “HLS Based IP Protection of Reusable Cores Using Biometric Fingerprint,” IEEE Letters of the Computer Society, vol. 3, no. 2, pp. 42-45, 1 July-Dec. 2020.

17. A. Sengupta and M. Rathor, “Protecting DSP Kernels using Robust Hologram based obfuscation”, IEEE Transactions on Consumer Electronics, vol. 65, no. 1, Feb 2019, pp. 99-108.

18. A. Sengupta and M. Rathor, “IP Core Steganography for Protecting DSP Kernels used in CE Systems,” IEEE Transactions on Consumer Electronics, vol. 65, no. 4, Nov. 2019, pp. 506 – 515.

19. A. Sengupta, M. Rathor, “Security of Functionally Obfuscated DSP core against Removal Attack using SHA-512 based Key Encryption Hardware”, IEEE Access Journal, vol. 7, pp. 4598-4610, 2019.

20.  M. Rathor and A. Sengupta, “Robust Logic locking for Securing Reusable DSP Cores,” IEEE Access, vol. 7, pp. 120052-120064, 2019.

21. M. Rathor, A. Sengupta, “Low-Cost Robust Anti-Removal Logic for Protecting Functionally Obfuscated DSP core against Removal Attack”,  IET Electronics Letters, vol. 55, no. 7, pp. 374-376, 2019.

22. A. Sengupta and M. Rathor, “Crypto based Dual phase Hardware Steganography for Securing IP cores,” IEEE Letters of the Computer Society, vol. 2, no. 4, pp. 32-35, 1 Dec. 2019.

Conferences (8):

1. A. Panzade, D. Kumar, M. Rathor and U. Chatterjee, "Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment", IEEE VLSI Design conference, Kolkata India, 2024.

2. M. Rathor, V. Mishra, U. Chatterjee, "Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers", Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, 2023.

3. A. Revskar, M. Rathor, U. Chatterjee, ''Dual-Tone Multi-Frequency Assisted Acoustic Side Channel Attack to Retrieve Dialled Call Log,'' in International Conference on Security, Privacy, and Applied Cryptography, Lecture Notes in Computer Science, Springer, vol 13783, 2022, India, https://doi.org/10.1007/978-3-031-22829-2_11.

4. M. Rathor and A. Sengupta, “Signature Biometric based Authentication of IP Cores for Secure Electronic Systems”, Proceedings of 7th IEEE International Symposium on Smart Electronic Systems (formerly iNIS), invited paper, India, Dec 2021, pp. 384-388.

5. M. Rathor, P. Sarkar, VK Mishra and A. Sengupta, “Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography”, Proceedings of 10th IEEE International Conference on Consumer Electronics- Berlin (ICCE Berlin), Germany, 2020, pp. 1-4.

6. M. Rathor and A. Sengupta, “Obfuscating DSP Hardware Accelerators in CE Systems Using Pseudo Operations Mixing”, Proceedings of 4th IEEE International Conference on Zooming Innovation in Consumer Electronics 2020 (ZINC 2020), Serbia, 2020, pp. 218-221.

7. M. Rathor and A. Sengupta, “Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic”, Proceedings of 9th IEEE International Conference on Consumer Electronics (ICCE)- Berlin, Berlin, 2019, pp. 1-5.

8. A. Sengupta and M. Rathor, “Improved Delay Estimation Model for Loop Based DSP Cores”, Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019, pp. 1-4. 

Patents Published (2):

1. M. Rathor, A System and Method for Embedding Voice Biometric Based Security Mark for Intellectual Property Cores Protection, Appl. no. 202311008221, 2023.

2. M. Rathor, V. Mishra, U. Chatterjee, A System and Method for Efficient Rounding Off Binary Floating-Point Numbers to Nearest Integers, Appl. no. 202311026634, 2023.

Book Chapters (8):

1.  A. Sengupta and M. Rathor,  "Introduction: Secured Co-processors for Machine Learning and DSP Applications using Biometrics", IET Book "Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors", 2023, ISBN-13: 978-1-83953-821-6.

2. M. Rathor, A. Sengupta "Particle Swarm Optimization driven DSE based Low Cost Hardware Security for Securing DSP IP Cores", Springer Book "Advances in Nature-inspired Cyber Security and Resilience", 2021, Invited Book Chapter, Print ISBN: 978-3-030-90707-5.

3. A. Sengupta and M. Rathor, “Designing Secured N-point DFT Hardware Accelerator using Obfuscation and Steganography”, IET Book: Secured Hardware Accelerators for DSP and Image processing applications, 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5.

4. A. Sengupta and M. Rathor, “Structural transformation and obfuscation frameworks for Data-intensive IPs”, IET Book: Secured Hardware Accelerators for DSP and Image processing applications, 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5.

5. A. Sengupta and M. Rathor, “Security of Functionally Obfuscated DSP cores”, IET Book: Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques, 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6.

6. A. Sengupta and M. Rathor, “Hologram based Structural Obfuscation for DSP Cores”, IET Book: Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques, 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6.

7. A. Sengupta and M. Rathor, “Hardware (IP) Watermarking during Behavioural Synthesis”, Springer Book: Behavioral Synthesis for Hardware Security, 2021, Invited Chapter (Eds.Srinivas Katkoori, Sheikh Ariful Islam), Print ISBN: 978-3-030-78840-7, Online ISBN: 978-3-030-78841-4.

8. A. Sengupta and M. Rathor, “Design Space Exploration of DSP hardware using Bacterial Foraging and Particle Swarm Optimization Algorithm for Power/Area-Delay Tradeoff”, IET Book: Low Power Nanoscale IC Design, Invited Book Chapter, 2020, Print ISBN: 978-981-15-7936-3.