Rcent Publications:
M. Rathor, "ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer, ACM Trans. Embed. Comput. Syst. 24, 1, Article 12 (January 2025), 26 pages. https://doi.org/10.1145/3701560.
A. Kamal, V. Mishra, S. Mittal, M. Rathor, C. Kumar and U. Chatterjee, "Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF,", in Proc. ASIAN-HOST, Japan, 2024, 10.1109/AsianHOST63913.2024.10838484.
A. Panzade, D. Kumar, M. Rathor and U. Chatterjee, "Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment", IEEE VLSI Design conference, Kolkata India, 2024.
M. Rathor, V. Mishra, U. Chatterjee, "Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers", Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, 2023.
M. Rathor, A. Sengupta, "Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-aided Trojan Attack", IEEE Embedded Systems Letters (ESL), 2023, doi: 10.1109/LES.2023.3327793.
M. Rathor, A. Anshul , A. Sengupta, "Securing Reusable IP Cores using Voice Biometric based Watermark," IEEE Transactions on Dependable and Secure Computing, vol. 21, no. 4, pp. 2735-2749, July-Aug. 2024, doi: 10.1109/TDSC.2023.3315780.
M. Rathor and G. P. Rathor, "Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature," IEEE Design & Test, Aug 2023, doi: 10.1109/MDAT.2023.3307576.
A. Sengupta, R. Chaurasia, M. Rathor, "HLS based Swarm Intelligence Driven Optimized Hardware IP Core for Linear Regression based Machine Learning", IET Journal of Engineering, Vol. 2023, issue: 8, Aug 2023.
A. Sengupta, M. Rathor, R. Chaurasia "Biometrics for Hardware Security and Trust: Discussion and Analysis", IEEE IT Professionals (ITPro), vol. 25, no. 4, pp. 36-44, July-Aug. 2023, doi: 10.1109/MITP.2023.3277594.
M. Rathor, A. Sengupta, R. Chaurasia, A. Anshul "Exploring Handwritten Signature Image Features for Hardware Security", IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 20, no. 5, pp. 3687-3698, 1 Sept.-Oct. 2023, doi: 10.1109/TDSC.2022.3218506.
M. Rathor, A. Anshul, K Bharath, R. Chaurasia , A. Sengupta, "Quadruple Phase Watermarking during High Level Synthesis for Securing Reusable Hardware IP Cores", Elsevier Journal on Computers and Electrical Engineering, Volume 105, 2023, 108476, ISSN 0045-7906, https://doi.org/10.1016/j.compeleceng.2022.108476.
A. Sengupta, M. Rathor, “Facial Biometric for Securing Hardware Accelerators,” IEEE Transactions on Very Large Scale Integration (VLSI), 2020, vol. 29, no. 1, pp. 112-123, 2021, doi: 10.1109/TVLSI.2020.3029245.
M. Rathor and A. Sengupta, “IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems,” IEEE Transactions on Consumer Electronics, vol. 66, no. 3, pp. 251-260, Aug. 2020.
A. Sengupta and M. Rathor, “Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems”, IEEE Transactions on Consumer Electronics, vol. 66, no. 2, May 2020, pp. 163-172.
A. Sengupta and M. Rathor, “Obfuscated Hardware Accelerators for Image Processing Filters-Application Specific and Functionally Reconfigurable Processors,” IEEE Transactions on Consumer Electronics, vol. 66, no. 4, pp. 386-395, Nov. 2020.
A. Sengupta, M. Rathor, “Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting”, IEEE Transactions on Very Large Scale Integration (VLSI), vol. 28, no. 9, pp. 1979-1992, Sept. 2020.
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