(Sept. 1992 ~ April 1998)
Degree: Doctor of Philosophy
(Sept. 1990 ~ July 1992)
Degree: Master of Engineering
Technical manager, MediaTek Inc, Hsin-Chu, Taiwan (January/2019 ~ September/2019)
Technical manager, Mstar Semiconductor, Hsin-Chu, Taiwan (March/2012 ~ December/2018)
Technical manager, Sunplus Technology Co., Ltd. Hsin-Chu, Taiwan ( July 2004 ~ Oct/2011)
Section manager, VIA technologies, Inc., Taipei, Taiwan (March 2001 ~ July 2004)
Engineer, Ali Corporation, Taipei, Taiwan (Nov. 2000 ~ March 2001)
1. Local voice control and voice assistant
Nowadays, voice control and voice assistant are commonly accomplished by sending the recorded voices to the cloud for making speech recognition and understanding. The results are then sending back to local devices for further processing, for example, controlling the local device or providing information. When the wireless connectivity is not good, however, the response would be not prompt enough for the purpose of controlling local devices. This task is to find a solution that processes the voice locally and understands the user’s control command as soon as possible. If the voice is not about to control local devices, it will then be sent to the cloud for further processing.
2. Sparse Neural Networks on FPGA
The size of the neural networks can be compressed in a large quantities. However, because of the scarcity of these compressed neural network, they may not be suitable to be executed or ran on GPUs. We are interested in analyzing the performance, cost, and power consumption of running the compressed neural networks on FPGAs, and finding ways to make improvement.
3. Defect detection and Classification
The PCB manufacturing is important as the consumer electronics products are indispensable for our everyday life. We are interested in reducing cost spending in manufacturing caused by the defects on PCB’s. We will examine methods that adopt deep learning algorithm to finding these kinds of defects.
1. Ching-Wen Ma and Ching-Cheng Teng, “Detection of Coherent Signals Using Weighted Subspace Smoothing,” IEEE Transactions on Antennas and Propagation, vol. 44, no. 2, Feb. 1996, pp. 179 – 187.
2. Ching-Wen Ma and Ching-Ching Teng, “Tracking a Near-Field Moving Target Using Fuzzy Neural Networks,” Fuzzy Sets and Systems, 2000, pp.365 –377.
3. Ching-Wen Ma and Ching-Cheng Teng, “Fuzzy Neural Network Approach for 2-D Direction Finding in Multipath Environments,” IEE Proceedings Radar, Sonar and Navigation, vol. 146, no. 2, April 1999, pp. 78 – 83.
4. Ching-Wen Ma and Ching-Cheng Teng, “ Detection of Coherent signals Using Weighted Subspace Smoothing,” Proceedings 1994 National Symposium on Telecommunications, Chia-Yi, Taiwan, R.O.C. pp. 7 – 11.
5. Ching-Wen Ma and Ching-Cheng Teng, “ The Noise-Dragging Phenomenon of IQML Algorithm for Direction-of-Arrival Estimation,” Proceedings 1995 International Symposium on Communicaitons, pp. 1147 – 1154.
6. Ching-Wen Ma and Ching-Cheng Teng, “Near-Field Direction Finding with A Fuzzy Neural Network,” Proceedings of 1996 Asian Fuzzy Systems Symposium, pp. 203 – 235.
7. Ching-Wen Ma and Ching-Cheng Teng, “Coherent Signal Detection Using Weigghted Subspace Smoothing,” Proceedings of 1997 International Symposium on Communicatins, pp.269 – 273.
8. Cryptographic device and secret key protection method
Patent number: 10110375
Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.
Type: Grant
Filed: May 15, 2014
Date of Patent: October 23, 2018
Assignee: MSTAR SEMICONDUCTOR, INC.
Inventor: Ching-Wen Ma
9. Decision feedback equalizer and control method thereof
Patent number: 9674012
Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.
Type: Grant
Filed: February 8, 2016
Date of Patent: June 6, 2017
Assignee: MStar Semiconductor, Inc.
Inventors: Ching-Wen Ma, Tai-Lai Tung
10. Method and device for calculating coefficients of feed-forward equalizer and feed-backward equalizer in decision feedback equalizer
Patent number: 9503292
Abstract: A method for calculating a feed forward equalizer coefficient of a feed forward equalizer in a minimum mean square error decision feedback equalizer (MMSE-DFE) based on a fast transversal recursive least squares (FT-RLS) algorithm is provided. The length of the feed-forward equalizer is LF, which is a positive integer. The method includes an outer iteration having an LF number of iterations. The outer iteration includes an inner iteration having an n number of iterations, where n is an integer between 0 and (LF?2).
Type: Grant
Filed: October 28, 2015
Date of Patent: November 22, 2016
Assignee: MSTAR SEMICONDUCTOR, INC.
Inventors: Ching-Wen Ma, Chih-Cheng Kuo, Tai-Lai Tung, Chih-Ching Chen
11. Circuit for generating tracking error signal
Patent number: 8254221
Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.
Type: Grant
Filed: January 24, 2012
Date of Patent: August 28, 2012
Assignee: Sunplus Technology Co., Ltd.
Inventors: Ching-Wen Ma, Yung-Chi Yang
12. Circuit for generating tracking error signal
Patent number: 8134895
Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.
Type: Grant
Filed: June 13, 2008
Date of Patent: March 13, 2012
Assignee: Sunplus Technology Co., Ltd.
Inventors: Ching-Wen Ma, Yung-Chi Yang
13. Automatic gain control loop with hysteresis switching
Patent number: 8112052
Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.
Type: Grant
Filed: July 14, 2010
Date of Patent: February 7, 2012
Assignee: Sunplus Technology Co., Ltd.
Inventor: Ching-Wen Ma
14. Control system for an optical storage device
Patent number: 8055981
Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.
Type: Grant
Filed: November 9, 2007
Date of Patent: November 8, 2011
Assignee: Sunplus Technology Co., Ltd.
Inventors: Ching-Wen Ma, Zheng-Xiong Chen, Shih-Hsien Liu
15. Error correction code decoder
Patent number: 7805662
Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.
Type: Grant
Filed: February 9, 2007
Date of Patent: September 28, 2010
Assignee: Sunplus Technology Co., Ltd.
Inventors: Ching-Wen Ma, Kuo-Ming Wang, Jia-Ping Chen
16. Timing recovery circuit
Patent number: 7187739
Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.
Type: Grant
Filed: May 16, 2003
Date of Patent: March 6, 2007
Assignee: Via Technologies, Inc.
Inventor: Ching-Wen Ma
17. Non-SDMA system with an SDMA method
Patent number: 6801514
Abstract: A communications system providing SDMA communication channels in a non-SDMA (non-spatial division multiple access) system and used in a specific area to establish wireless communications with mobile stations in the area comprises a smart antenna to establish wireless communications with the mobile stations, a base station controller managing transmissions and receiving information between every mobile station and an outgoing communications network, a plurality of base transceiver stations electrically connected with the base station controller, each of them establishing the wireless communications between the mobile stations and the base station controller, and a spatial spectrum management system connected between the smart antenna and the base transceiver stations.
Type: Grant
Filed: February 6, 2001
Date of Patent: October 5, 2004
Assignee: BenQ Corporation
Inventor: Ching-Wen Ma
18. Method and device for adjusting reference level
Patent number: 7200092
Abstract: A method for adjusting a reference level of an analog signal from a plurality of periodically sampled points includes the following steps. Firstly, a first level shift from an preliminary reference level to the last second sampled point within a specified period and a second level shift from the preliminary reference level to the last sampled point within the specified period is determined when one of a first level of the last second sampled point and a second level of the last sampled point is higher than the preliminary reference level and the other is lower than the preliminary reference level. Then, the preliminary reference level is moved toward the first level when an absolute value of the first level shift is greater than an absolute value of the second level shift, and the preliminary reference level is moved toward the second level when the absolute value of the first level shift is less than the absolute value of the second level shift, thereby defining an adjusted reference level.
Type: Grant
Filed: September 25, 2003
Date of Patent: April 3, 2007
Assignee: Via Technologies, Inc.
Inventor: William Mar
19. Viterbi decoding device and method for processing multi-data input into multi-data output
Patent number: 7185269
Abstract: In a Viterbi decoder, a branch metric calculating operation of a series of received input data is performed according to different sets of target levels to realize a plurality of branch metric values, wherein said target level sets are not identical. Accumulative operations of the branch metric values are performed, respectively, and the plurality of accumulated values are compared in groups. A plurality of control signals and a plurality of least accumulated values are outputted according comparing results of the accumulated values. The least accumulated values are received and stored, and then fed back for next accumulation operations. A plurality of possible output-data state transition tracks are recoded in response to the control signals. The output data are determined according to the least accumulated values and output-data state transition tracks.
Type: Grant
Filed: July 2, 2003
Date of Patent: February 27, 2007
Assignee: VIA Optical Solution, Inc.
Inventors: William Mar, Kelven Cheng
20. Method and related apparatus for locking phase with estimated rate modified by rate dithering
Patent number: 7085949
Abstract: A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.
Type: Grant
Filed: September 14, 2003
Date of Patent: August 1, 2006
Assignee: VIA Technologies Inc.
Inventors: William Mar, Luke Wen
21. Method and device for correcting signal
Patent number: 6737998
Abstract: A method for correcting an analog signal to target levels is provided. Firstly, the analog signal is periodically sampled to obtain a plurality of sampled points. Then, levels of the sampled points are compared with a threshold value to find a set of sequentially sampled points including a head and a tail ones, each having a first comparing result with the threshold value, and the other intermediate ones, each having a second comparing result with the threshold value. Then, one of the set of sequentially sampled points, which has the second comparing result with the threshold value, is adjusted to one of the target levels. A device for correcting an analog signal to target levels is also provided.
Type: Grant
Filed: May 12, 2003
Date of Patent: May 18, 2004
Assignee: Via Technologies, Inc.
Inventor: William Mar
22. Method and device for recovering RLL constrained data to be decoded
Patent number: 6664904
Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.
Type: Grant
Filed: July 30, 2002
Date of Patent: December 16, 2003
Assignee: Via Optical Solution, Inc.
Inventors: William Mar, Luke Wen
23. Method for recovering data and control chip utilizing the same
Patent number: 7065027
Abstract: A method for locating an electric level distribution range of sampled signals is provided. The electric level distribution range includes a plurality of reference levels. Firstly, a plurality of initial values are provided. Then, each of the sampled signals is corresponded to one of the plurality of initial values, which is closest thereto. Then, the initial values corresponded are and adjusted by the sampled signals according to a predetermined operation, thereby realizing the reference levels. A method for recovering data from an optical storage medium is also provided. The signals associated with data from an optical storage medium are firstly sampled. Then, an electric level distribution range of the sampled signals is located. Afterwards, the sampled signals are decoded to recover data according to the electric level distribution range.
Type: Grant
Filed: April 22, 2003
Date of Patent: June 20, 2006
Assignee: Via Technologies, Inc.
Inventors: Kalman Cheng, Ching-Wen Mar
